license = 'gplv2+'
inputs = ['logic']
outputs = ['pjon_link']
- tags = ['Embedded']
+ tags = ['Embedded/industrial']
channels = (
{'id': 'data' , 'name': 'DATA', 'desc': 'Single wire data'},
)
# for bit widths (tolerance margin).
# Get times in microseconds.
- self.data_width, self.pad_width = self.mode_times[self.options['mode']]
+ mode_times = self.mode_times[self.options['mode']]
+ mode_times = [t * 1.0 for t in mode_times]
+ self.data_width, self.pad_width = mode_times
self.byte_width = self.pad_width + 9 * self.data_width
self.add_idle_width = self.options['idle_add_us']
self.idle_width = self.byte_width + self.add_idle_width
is_short = bit_level and self.span_is_short(span)
if is_pad:
- ss, es = last_snum, curr_snum
+ # BEWARE! Use ss value of last edge (genuinely seen, or
+ # inserted after a DATA byte) for PAD bit annotations.
+ ss, es = self.edges[-2], curr_snum
texts = ['PAD', '{:d}'.format(bit_level)]
self.putg(ss, es, [ANN_PAD_BIT, texts])
self.symbols_append(ss, es, 'PAD_BIT', bit_level)
# the transmitter's and the sender's timings differ within a
# margin, and the transmitter may hold the last DATA bit's
# HIGH level for a little longer.
+ #
+ # When no falling edge is seen within the maximum tolerance
+ # for the last DATA bit, then this could be the combination
+ # of a HIGH DATA bit and a PAD bit without a LOW in between.
+ # Fake an edge in that case, to re-use existing code paths.
+ # Make sure to keep referencing times to the last SYNC pad's
+ # falling edge. This is the last reliable condition we have.
if curr_level:
hold = self.hold_high_width
curr_level, = self.wait([{PIN_DATA: 'l'}, {'skip': int(hold)}])
self.carrier_check(curr_level, self.samplenum)
+ if self.matched[1]:
+ self.edges.append(curr_snum)
+ curr_level = 1 - curr_level
curr_snum = self.samplenum
# Get the byte value from the bits (when available).