parallel: Make CLK probe optional.

[libsigrokdecode.git] / decoders / parallel / pd.py

diff --git a/decoders/parallel/pd.py b/decoders/parallel/pd.py
index 9c203543f21a65593df2eea5b753dc1a1c32b6f4..c31718fb4efc371fadfe17d056425a40d805e988 100644 (file)
--- a/decoders/parallel/pd.py
+++ b/decoders/parallel/pd.py
@@ -57,7 +57,7 @@ Packet:
 '''
 
 def probe_list(num_probes):
-    l = []
+    l = [{'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'}]
     for i in range(num_probes):
         d = {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data line %d' % i}
         l.append(d)
@@ -72,9 +72,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['parallel']
-    probes = [
-        {'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'},
-    ]
+    probes = []
     optional_probes = probe_list(8)
     options = {
         'clock_edge': ['Clock edge to sample on', 'rising'],
@@ -98,13 +96,10 @@ class Decoder(srd.Decoder):
         self.first = True
         self.state = 'IDLE'
 
-    def start(self, metadata):
+    def start(self):
         self.out_proto = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
-    def report(self):
-        pass
-
     def putpb(self, data):
         self.put(self.ss_item, self.es_item, self.out_proto, data)
 
@@ -190,7 +185,10 @@ class Decoder(srd.Decoder):
 
             # State machine.
             if self.state == 'IDLE':
-                self.find_clk_edge(pins[0], pins[1:])
+                if pins[0] not in (0, 1):
+                    self.handle_bits(pins[1:])
+                else:
+                    self.find_clk_edge(pins[0], pins[1:])
             else:
                 raise Exception('Invalid state: %s' % self.state)