can: introduce fast bitrate

[libsigrokdecode.git] / decoders / can / pd.py

diff --git a/decoders/can/pd.py b/decoders/can/pd.py
index 2663b7d7c98f25a7d5a63784d09b6d5ce2147ec3..5d27b28d23105db1096d813ddd782dd986f9611d 100644 (file)
--- a/decoders/can/pd.py
+++ b/decoders/can/pd.py
@@ -37,7 +37,8 @@ class Decoder(srd.Decoder):
         {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'},
     )
     options = (
-        {'id': 'bitrate', 'desc': 'Bitrate (bits/s)', 'default': 1000000},
+        {'id': 'nominal_bitrate', 'desc': 'Nominal Bitrate (bits/s)', 'default': 1000000},
+        {'id': 'fast_bitrate', 'desc': 'Fast Bitrate (bits/s)', 'default': 2000000},
         {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0},
     )
     annotations = (
@@ -65,7 +66,6 @@ class Decoder(srd.Decoder):
         ('fields', 'Fields', tuple(range(15))),
         ('warnings', 'Warnings', (16,)),
     )
-    fd = False
 
     def __init__(self):
         self.reset()
@@ -83,7 +83,7 @@ class Decoder(srd.Decoder):
     def metadata(self, key, value):
         if key == srd.SRD_CONF_SAMPLERATE:
             self.samplerate = value
-            self.bit_width = float(self.samplerate) / float(self.options['bitrate'])
+            self.bit_width = float(self.samplerate) / float(self.options['nominal_bitrate'])
             self.sample_point = (self.bit_width / 100.0) * self.options['sample_point']
 
     # Generic helper for CAN bit annotations.
@@ -99,6 +99,10 @@ class Decoder(srd.Decoder):
     def put12(self, data):
         self.putg(self.ss_bit12, self.ss_bit12, data)
 
+    # Single-CAN-bit annotation using the samplenum of CAN bit 32.
+    def put32(self, data):
+        self.putg(self.ss_bit32, self.ss_bit32, data)
+
     # Multi-CAN-bit annotation from self.ss_block to current samplenum.
     def putb(self, data):
         self.putg(self.ss_block, self.samplenum, data)
@@ -112,7 +116,10 @@ class Decoder(srd.Decoder):
         self.last_databit = 999 # Positive value that bitnum+x will never match
         self.ss_block = None
         self.ss_bit12 = None
+        self.ss_bit32 = None
         self.ss_databytebits = []
+        self.fd = False
+        self.rtr = None
 
     # Poor man's clock synchronization. Use signal edges which change to
     # dominant state in rather simple ways. This naive approach is neither
@@ -333,11 +340,13 @@ class Decoder(srd.Decoder):
 
         # Remember start of RTR (see below).
         if bitnum == 32:
-            rtr = 'remote' if can_rx == 1 else 'data'
-            self.putx([8, ['Remote transmission request: %s frame' % rtr,
-                           'RTR: %s frame' % rtr, 'RTR']])
+            self.ss_bit32 = self.samplenum
+            self.rtr = can_rx
 
-            # TODO: annotate as R1 on FD frame
+            if not self.fd:
+               rtr = 'remote' if can_rx == 1 else 'data'
+               self.putx([8, ['Remote transmission request: %s frame' % rtr,
+                              'RTR: %s frame' % rtr, 'RTR']])
 
         # Bit 33: RB1 (reserved bit)
         elif bitnum == 33:
@@ -347,6 +356,9 @@ class Decoder(srd.Decoder):
                 self.dlc_start = 37
                 self.putx([7, ['Flexible Data Format: %d' % can_rx,
                                'FDF: %d' % can_rx, 'FDF']])
+
+                self.put32([7, ['Reserved bit 1: %d' % self.rtr,
+                                'RB1: %d' % self.rtr, 'RB1']])
             else:
                 self.putx([7, ['Reserved bit 1: %d' % can_rx,
                                'RB1: %d' % can_rx, 'RB1']])