## along with this program; if not, see <http://www.gnu.org/licenses/>.
##
+from common.srdhelper import bitpack
import sigrokdecode as srd
class SamplerateError(Exception):
desc = 'Field bus protocol for distributed realtime control.'
license = 'gplv2+'
inputs = ['logic']
- outputs = []
+ outputs = ['can']
tags = ['Automotive']
channels = (
{'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'},
{'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0},
)
annotations = (
- ('data', 'CAN payload data'),
+ ('data', 'Payload data'),
('sof', 'Start of frame'),
('eof', 'End of frame'),
('id', 'Identifier'),
('ack-slot', 'ACK slot'),
('ack-delimiter', 'ACK delimiter'),
('stuff-bit', 'Stuff bit'),
- ('warnings', 'Human-readable warnings'),
+ ('warning', 'Warning'),
('bit', 'Bit'),
)
annotation_rows = (
def start(self):
self.out_ann = self.register(srd.OUTPUT_ANN)
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
def set_bit_rate(self, bitrate):
self.bit_width = float(self.samplerate) / float(bitrate)
def putb(self, data):
self.putg(self.ss_block, self.samplenum, data)
+ def putpy(self, data):
+ self.put(self.ss_packet, self.es_packet, self.out_python, data)
+
def reset_variables(self):
self.state = 'IDLE'
self.sof = self.frame_type = self.dlc = None
self.ss_bit12 = None
self.ss_bit32 = None
self.ss_databytebits = []
+ self.frame_bytes = []
+ self.rtr_type = None
self.fd = False
self.rtr = None
self.dom_edge_snum = self.samplenum
self.dom_edge_bcount = self.curbit
- def bit_sampled(self):
- # EMPTY
- pass
-
# Determine the position of the next desired bit's sample point.
def get_sample_point(self, bitnum):
samplenum = self.dom_edge_snum
x = self.last_databit + 1
crc_bits = self.bits[x:x + self.crc_len + 1]
- self.crc = int(''.join(str(d) for d in crc_bits), 2)
+ bits = crc_bits
+ bits.reverse()
+ self.crc = bitpack(bits)
self.putb([11, ['%s sequence: 0x%04x' % (crc_type, self.crc),
'%s: 0x%04x' % (crc_type, self.crc), '%s' % crc_type]])
if not self.is_valid_crc(crc_bits):
self.putb([2, ['End of frame', 'EOF', 'E']])
if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]:
self.putb([16, ['End of frame (EOF) must be 7 recessive bits']])
+ self.es_packet = self.samplenum
+ py_data = tuple([self.frame_type, self.fullid, self.rtr_type,
+ self.dlc, self.frame_bytes])
+ self.putpy(py_data)
self.reset_variables()
return True
rtr = 'remote' if self.bits[12] == 1 else 'data'
self.put12([8, ['Remote transmission request: %s frame' % rtr,
'RTR: %s frame' % rtr, 'RTR']])
+ self.rtr_type = rtr
self.dlc_start = 15
if bitnum == 15 and self.fd:
# Bits 15-18: Data length code (DLC), in number of bytes (0-8).
elif bitnum == self.dlc_start + 3:
- self.dlc = int(''.join(str(d) for d in self.bits[self.dlc_start:self.dlc_start + 4]), 2)
+ bits = self.bits[self.dlc_start:self.dlc_start + 4]
+ bits.reverse()
+ self.dlc = bitpack(bits)
self.putb([10, ['Data length code: %d' % self.dlc,
'DLC: %d' % self.dlc, 'DLC']])
self.last_databit = self.dlc_start + 3 + (dlc2len(self.dlc) * 8)
self.ss_databytebits.append(self.samplenum) # Last databyte bit.
for i in range(dlc2len(self.dlc)):
x = self.dlc_start + 4 + (8 * i)
- b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2)
+ bits = self.bits[x:x + 8]
+ bits.reverse()
+ b = bitpack(bits)
+ self.frame_bytes.append(b)
ss = self.ss_databytebits[i * 8]
es = self.ss_databytebits[((i + 1) * 8) - 1]
self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
# Bits 14-31: Extended identifier (EID[17..0])
elif bitnum == 31:
- self.eid = int(''.join(str(d) for d in self.bits[14:]), 2)
+ bits = self.bits[14:]
+ bits.reverse()
+ self.eid = bitpack(bits)
s = '%d (0x%x)' % (self.eid, self.eid)
self.putb([4, ['Extended Identifier: %s' % s,
'Extended ID: %s' % s, 'Extended ID', 'EID']])
self.rtr = can_rx
if not self.fd:
- rtr = 'remote' if can_rx == 1 else 'data'
- self.putx([8, ['Remote transmission request: %s frame' % rtr,
+ rtr = 'remote' if can_rx == 1 else 'data'
+ self.putx([8, ['Remote transmission request: %s frame' % rtr,
'RTR: %s frame' % rtr, 'RTR']])
+ self.rtr_type = rtr
# Bit 33: RB1 (reserved bit)
elif bitnum == 33:
# Bits 35-38: Data length code (DLC), in number of bytes (0-8).
elif bitnum == self.dlc_start + 3:
- self.dlc = int(''.join(str(d) for d in self.bits[self.dlc_start:self.dlc_start + 4]), 2)
+ bits = self.bits[self.dlc_start:self.dlc_start + 4]
+ bits.reverse()
+ self.dlc = bitpack(bits)
self.putb([10, ['Data length code: %d' % self.dlc,
'DLC: %d' % self.dlc, 'DLC']])
self.last_databit = self.dlc_start + 3 + (dlc2len(self.dlc) * 8)
self.ss_databytebits.append(self.samplenum) # Last databyte bit.
for i in range(dlc2len(self.dlc)):
x = self.dlc_start + 4 + (8 * i)
- b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2)
+ bits = self.bits[x:x + 8]
+ bits.reverse()
+ b = bitpack(bits)
+ self.frame_bytes.append(b)
ss = self.ss_databytebits[i * 8]
es = self.ss_databytebits[((i + 1) * 8) - 1]
self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
# Bit 0: Start of frame (SOF) bit
if bitnum == 0:
+ self.ss_packet = self.samplenum
self.putx([1, ['Start of frame', 'SOF', 'S']])
if can_rx != 0:
self.putx([16, ['Start of frame (SOF) must be a dominant bit']])
# Bits 1-11: Identifier (ID[10..0])
# The bits ID[10..4] must NOT be all recessive.
elif bitnum == 11:
- self.id = int(''.join(str(d) for d in self.bits[1:]), 2)
+ bits = self.bits[1:]
+ bits.reverse()
+ # BEWARE! Clobbers the decoder's .id field!
+ self.id = bitpack(bits)
+ self.fullid = self.id
s = '%d (0x%x)' % (self.id, self.id),
self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']])
if (self.id & 0x7f0) == 0x7f0:
self.dom_edge_seen()
if self.matched[0]:
self.handle_bit(can_rx)
- self.bit_sampled()