+#define MAX_RENUM_DELAY_MS 3000
+
+#define DEFAULT_VOLTAGE 2
+#define DEFAULT_SAMPLERATE SR_MHZ(8)
+
+#define NUM_CHANNELS 2
+
+#define SAMPLERATE_VALUES \
+ SR_MHZ(48), SR_MHZ(30), SR_MHZ(24), \
+ SR_MHZ(16), SR_MHZ(8), SR_MHZ(4), \
+ SR_MHZ(1), SR_KHZ(500), SR_KHZ(200), \
+ SR_KHZ(100),
+
+#define SAMPLERATE_REGS \
+ 48, 30, 24, 16, 8, 4, 1, 50, 20, 10,
+
+#define VDIV_VALUES \
+ { 100, 1000 }, \
+ { 250, 1000 }, \
+ { 500, 1000 }, \
+ { 1, 1 },
+
+#define VDIV_REG \
+ 10, 5, 2, 1,
+
+#define VDIV_MULTIPLIER 10
+
+/* Weird flushing needed for filtering glitch away. */
+#define FLUSH_PACKET_SIZE 2600
+
+#define MIN_PACKET_SIZE 600
+#define MAX_PACKET_SIZE (12 * 1024 * 1024)
+
+#define HANTEK_EP_IN 0x86
+#define USB_INTERFACE 0
+#define USB_CONFIGURATION 1
+
+enum control_requests {
+ VDIV_CH1_REG = 0xe0,
+ VDIV_CH2_REG = 0xe1,
+ SAMPLERATE_REG = 0xe2,
+ TRIGGER_REG = 0xe3,
+ CHANNELS_REG = 0xe4,
+};
+
+enum states {
+ IDLE,
+ FLUSH,
+ CAPTURE,
+ STOPPING,
+};
+
+struct hantek_6xxx_profile {
+ /* VID/PID after cold boot */
+ uint16_t orig_vid;
+ uint16_t orig_pid;
+ /* VID/PID after firmware upload */
+ uint16_t fw_vid;
+ uint16_t fw_pid;
+ const char *vendor;
+ const char *model;
+ const char *firmware;
+};
+