+ def putpm(self, data):
+ s, h = self.samplenum, self.halfbit
+ self.put(self.ss_block - h, s + h, self.out_python, data)
+
+ def putm(self, data):
+ s, h = self.samplenum, self.halfbit
+ self.put(self.ss_block - h, s + h, self.out_ann, data)
+
+ def putpb(self, data):
+ s, h = self.samplenum, self.halfbit
+ self.put(s - h, s + h, self.out_python, data)
+
+ def putb(self, data):
+ s, h = self.samplenum, self.halfbit
+ self.put(s - h, s + h, self.out_ann, data)
+
+ def set_new_target_samplenum(self):
+ bitpos = self.ss_sop + (self.bitwidth / 2)
+ bitpos += self.bitnum * self.bitwidth
+ self.samplenum_target = int(bitpos)
+
+ def wait_for_sop(self, sym):
+ # Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
+ if sym != 'K':
+ self.oldsym = sym
+ return
+ self.ss_sop = self.samplenum
+ self.set_new_target_samplenum()
+ self.putpx(['SOP', None])
+ self.putx([1, ['SOP']])
+ self.state = 'GET BIT'
+
+ def handle_bit(self, sym, b):
+ if self.consecutive_ones == 6 and b == '0':
+ # Stuff bit.
+ self.putpb(['STUFF BIT', None])
+ self.putb([4, ['SB: %s' % b]])
+ self.putb([0, ['%s' % sym]])
+ self.consecutive_ones = 0
+ else:
+ # Normal bit (not a stuff bit).
+ self.putpb(['BIT', b])
+ self.putb([3, ['%s' % b]])
+ self.putb([0, ['%s' % sym]])
+ if b == '1':
+ self.consecutive_ones += 1
+ else:
+ self.consecutive_ones = 0
+
+ def get_eop(self, sym):
+ # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
+ self.syms.append(sym)
+ self.putpb(['SYM', sym])
+ self.putb([0, ['%s' % sym]])
+ self.bitnum += 1
+ self.set_new_target_samplenum()
+ self.oldsym = sym
+ if self.syms[-2:] == ['SE0', 'J']:
+ # Got an EOP.
+ self.putpm(['EOP', None])
+ self.putm([2, ['EOP']])
+ self.bitnum, self.syms, self.state = 0, [], 'IDLE'
+ self.consecutive_ones = 0
+
+ def get_bit(self, sym):
+ if sym == 'SE0':
+ # Start of an EOP. Change state, run get_eop() for this bit.
+ self.state = 'GET EOP'
+ self.ss_block = self.samplenum
+ self.get_eop(sym)
+ return
+ self.syms.append(sym)
+ self.putpb(['SYM', sym])
+ b = '0' if self.oldsym != sym else '1'
+ self.handle_bit(sym, b)
+ self.bitnum += 1
+ self.set_new_target_samplenum()
+ self.oldsym = sym
+