- self.cs_was_deasserted_during_data_word = 0
- self.oldcs = -1
- self.oldpins = None
-
- def start(self, metadata):
- self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
-
- def report(self):
- return 'SPI: %d bytes received' % self.bytesreceived
-
- def decode(self, ss, es, data):
- # TODO: Either MISO or MOSI could be optional. CS# is optional.
- for (self.samplenum, pins) in data:
-
- # Ignore identical samples early on (for performance reasons).
- if self.oldpins == pins:
- continue
- self.oldpins, (miso, mosi, sck, cs) = pins, pins
-
- if self.oldcs != cs:
- # Send all CS# pin value changes.
- self.put(self.samplenum, self.samplenum, self.out_proto,
- ['CS-CHANGE', self.oldcs, cs])
- self.put(self.samplenum, self.samplenum, self.out_ann,
- [0, ['CS-CHANGE: %d->%d' % (self.oldcs, cs)]])
- self.oldcs = cs
-
- # Ignore sample if the clock pin hasn't changed.
- if sck == self.oldsck:
- continue
-
- self.oldsck = sck
-
- # Sample data on rising/falling clock edge (depends on mode).
- mode = spi_mode[self.options['cpol'], self.options['cpha']]
- if mode == 0 and sck == 0: # Sample on rising clock edge
- continue
- elif mode == 1 and sck == 1: # Sample on falling clock edge
- continue
- elif mode == 2 and sck == 1: # Sample on falling clock edge
- continue
- elif mode == 3 and sck == 0: # Sample on rising clock edge
- continue
-
- # If this is the first bit, save its sample number.
- if self.bitcount == 0:
- self.start_sample = self.samplenum
- active_low = (self.options['cs_polarity'] == 'active-low')
- deasserted = cs if active_low else not cs
- if deasserted:
- self.cs_was_deasserted_during_data_word = 1
-
- ws = self.options['wordsize']
-
- # Receive MOSI bit into our shift register.
- if self.options['bitorder'] == 'msb-first':
- self.mosidata |= mosi << (ws - 1 - self.bitcount)
- else:
- self.mosidata |= mosi << self.bitcount
+ self.ss_transfer = -1
+ self.cs_was_deasserted = False
+ self.have_cs = self.have_miso = self.have_mosi = None
+
+ def start(self):
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
+ self.out_ann = self.register(srd.OUTPUT_ANN)
+ self.out_binary = self.register(srd.OUTPUT_BINARY)
+ self.out_bitrate = self.register(srd.OUTPUT_META,
+ meta=(int, 'Bitrate', 'Bitrate during transfers'))
+ self.bw = (self.options['wordsize'] + 7) // 8
+
+ def metadata(self, key, value):
+ if key == srd.SRD_CONF_SAMPLERATE:
+ self.samplerate = value
+
+ def putw(self, data):
+ self.put(self.ss_block, self.samplenum, self.out_ann, data)
+
+ def putdata(self):
+ # Pass MISO and MOSI bits and then data to the next PD up the stack.
+ so = self.misodata if self.have_miso else None
+ si = self.mosidata if self.have_mosi else None
+ so_bits = self.misobits if self.have_miso else None
+ si_bits = self.mosibits if self.have_mosi else None
+
+ if self.have_miso:
+ ss, es = self.misobits[-1][1], self.misobits[0][2]
+ bdata = so.to_bytes(self.bw, byteorder='big')
+ self.put(ss, es, self.out_binary, [0, bdata])
+ if self.have_mosi:
+ ss, es = self.mosibits[-1][1], self.mosibits[0][2]
+ bdata = si.to_bytes(self.bw, byteorder='big')
+ self.put(ss, es, self.out_binary, [1, bdata])
+
+ self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
+ self.put(ss, es, self.out_python, ['DATA', si, so])
+
+ if self.have_miso:
+ self.misobytes.append(Data(ss=ss, es=es, val=so))
+ if self.have_mosi:
+ self.mosibytes.append(Data(ss=ss, es=es, val=si))
+
+ # Bit annotations.
+ if self.have_miso:
+ for bit in self.misobits:
+ self.put(bit[1], bit[2], self.out_ann, [2, ['%d' % bit[0]]])
+ if self.have_mosi:
+ for bit in self.mosibits:
+ self.put(bit[1], bit[2], self.out_ann, [3, ['%d' % bit[0]]])
+
+ # Dataword annotations.
+ if self.have_miso:
+ self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]])
+ if self.have_mosi:
+ self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]])
+
+ def reset_decoder_state(self):
+ self.misodata = 0 if self.have_miso else None
+ self.mosidata = 0 if self.have_mosi else None
+ self.misobits = [] if self.have_miso else None
+ self.mosibits = [] if self.have_mosi else None
+ self.bitcount = 0