+ def handle_bit(self, miso, mosi, sck, cs):
+ # If this is the first bit, save its sample number.
+ if self.bitcount == 0:
+ self.startsample = self.samplenum
+ if self.have_cs:
+ active_low = (self.options['cs_polarity'] == 'active-low')
+ deasserted = cs if active_low else not cs
+ if deasserted:
+ self.cs_was_deasserted_during_data_word = 1
+
+ ws = self.options['wordsize']
+
+ # Receive MOSI bit into our shift register.
+ if self.options['bitorder'] == 'msb-first':
+ self.mosidata |= mosi << (ws - 1 - self.bitcount)
+ else:
+ self.mosidata |= mosi << self.bitcount
+
+ # Receive MISO bit into our shift register.
+ if self.options['bitorder'] == 'msb-first':
+ self.misodata |= miso << (ws - 1 - self.bitcount)
+ else:
+ self.misodata |= miso << self.bitcount
+
+ self.bitcount += 1
+
+ # Continue to receive if not enough bits were received, yet.
+ if self.bitcount != ws:
+ return
+
+ self.putpw(['DATA', self.mosidata, self.misodata])
+ self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]])
+ self.putw([1, ['%02X' % self.misodata]])
+ self.putw([2, ['%02X' % self.mosidata]])
+
+ if self.cs_was_deasserted_during_data_word:
+ self.putw([3, ['CS# was deasserted during this data word!']])
+
+ # Reset decoder state.
+ self.mosidata = self.misodata = self.bitcount = 0
+
+ # Keep stats for summary.
+ self.bytesreceived += 1
+
+ def find_clk_edge(self, miso, mosi, sck, cs):
+ if self.have_cs and self.oldcs != cs:
+ # Send all CS# pin value changes.
+ self.put(self.samplenum, self.samplenum, self.out_proto,
+ ['CS-CHANGE', self.oldcs, cs])
+ self.oldcs = cs
+ # Reset decoder state when CS# changes (and the CS# pin is used).
+ self.mosidata = self.misodata = self.bitcount= 0
+
+ # Ignore sample if the clock pin hasn't changed.
+ if sck == self.oldsck:
+ return
+
+ self.oldsck = sck
+
+ # Sample data on rising/falling clock edge (depends on mode).
+ mode = spi_mode[self.options['cpol'], self.options['cpha']]
+ if mode == 0 and sck == 0: # Sample on rising clock edge
+ return
+ elif mode == 1 and sck == 1: # Sample on falling clock edge
+ return
+ elif mode == 2 and sck == 1: # Sample on falling clock edge
+ return
+ elif mode == 3 and sck == 0: # Sample on rising clock edge
+ return
+
+ # Found the correct clock edge, now get the SPI bit(s).
+ self.handle_bit(miso, mosi, sck, cs)
+