##
-## This file is part of the sigrok project.
+## This file is part of the libsigrokdecode project.
##
-## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2011-2014 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-# UART protocol decoder
-
import sigrokdecode as srd
+'''
+OUTPUT_PYTHON format:
+
+UART packet:
+[<packet-type>, <rxtx>, <packet-data>]
+
+This is the list of <packet-type>s and their respective <packet-data>:
+ - 'STARTBIT': The data is the (integer) value of the start bit (0/1).
+ - 'DATA': The data is the (integer) value of the UART data. Valid values
+ range from 0 to 512 (as the data can be up to 9 bits in size).
+ - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1).
+ - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1).
+ - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1).
+ - 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1).
+ - 'PARITY ERROR': The data is a tuple with two entries. The first one is
+ the expected parity value, the second is the actual parity value.
+ - TODO: Frame error?
+
+The <rxtx> field is 0 for RX packets, 1 for TX packets.
+'''
+
# Used for differentiating between the two data directions.
RX = 0
TX = 1
-# Annotation feed formats
-ANN_ASCII = 0
-ANN_DEC = 1
-ANN_HEX = 2
-ANN_OCT = 3
-ANN_BITS = 4
-
# Given a parity type to check (odd, even, zero, one), the value of the
# parity bit, the value of the data, and the length of the data (5-9 bits,
# usually 8 bits) return True if the parity is correct, False otherwise.
license = 'gplv2+'
inputs = ['logic']
outputs = ['uart']
- probes = [
+ probes = []
+ optional_probes = [
# Allow specifying only one of the signals, e.g. if only one data
# direction exists (or is relevant).
{'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
{'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
]
- optional_probes = []
options = {
'baudrate': ['Baud rate', 115200],
'num_data_bits': ['Data bits', 8], # Valid: 5-9.
'parity_check': ['Check parity?', 'yes'], # TODO: Bool supported?
'num_stop_bits': ['Stop bit(s)', '1'], # String! 0, 0.5, 1, 1.5.
'bit_order': ['Bit order', 'lsb-first'],
+ 'format': ['Data format', 'ascii'], # ascii/dec/hex/oct/bin
# TODO: Options to invert the signal(s).
}
annotations = [
- ['ASCII', 'Data bytes as ASCII characters'],
- ['Decimal', 'Databytes as decimal, integer values'],
- ['Hex', 'Data bytes in hex format'],
- ['Octal', 'Data bytes as octal numbers'],
- ['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
+ ['rx-data', 'RX data'],
+ ['tx-data', 'TX data'],
+ ['rx-start', 'RX start bits'],
+ ['tx-start', 'TX start bits'],
+ ['rx-parity-ok', 'RX parity OK bits'],
+ ['tx-parity-ok', 'TX parity OK bits'],
+ ['rx-parity-err', 'RX parity error bits'],
+ ['tx-parity-err', 'TX parity error bits'],
+ ['rx-stop', 'RX stop bits'],
+ ['tx-stop', 'TX stop bits'],
+ ['rx-warnings', 'RX warnings'],
+ ['tx-warnings', 'TX warnings'],
]
+ annotation_rows = (
+ ('rx-data', 'RX', (0, 2, 4, 6, 8)),
+ ('tx-data', 'TX', (1, 3, 5, 7, 9)),
+ ('rx-warnings', 'RX warnings', (10,)),
+ ('tx-warnings', 'TX warnings', (11,)),
+ )
+ binary = (
+ ('rx', 'RX dump'),
+ ('tx', 'TX dump'),
+ ('rxtx', 'RX/TX dump'),
+ )
def putx(self, rxtx, data):
- self.put(self.startsample[rxtx], self.samplenum - 1, self.out_ann, data)
+ s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
+ self.put(s - halfbit, self.samplenum + halfbit, self.out_ann, data)
+
+ def putg(self, data):
+ s, halfbit = self.samplenum, int(self.bit_width / 2)
+ self.put(s - halfbit, s + halfbit, self.out_ann, data)
+
+ def putp(self, data):
+ s, halfbit = self.samplenum, int(self.bit_width / 2)
+ self.put(s - halfbit, s + halfbit, self.out_python, data)
+
+ def putbin(self, rxtx, data):
+ s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
+ self.put(s - halfbit, self.samplenum + halfbit, self.out_bin, data)
def __init__(self, **kwargs):
+ self.samplerate = None
self.samplenum = 0
self.frame_start = [-1, -1]
self.startbit = [-1, -1]
self.stopbit1 = [-1, -1]
self.startsample = [-1, -1]
self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
- self.oldbit = [None, None]
- self.oldpins = None
+ self.oldbit = [1, 1]
+ self.oldpins = [1, 1]
- def start(self, metadata):
- self.samplerate = metadata['samplerate']
- self.out_proto = self.add(srd.OUTPUT_PROTO, 'uart')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'uart')
+ def start(self):
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
+ self.out_bin = self.register(srd.OUTPUT_BINARY)
+ self.out_ann = self.register(srd.OUTPUT_ANN)
- # The width of one UART bit in number of samples.
- self.bit_width = \
- float(self.samplerate) / float(self.options['baudrate'])
-
- def report(self):
- pass
+ def metadata(self, key, value):
+ if key == srd.SRD_CONF_SAMPLERATE:
+ self.samplerate = value;
+ # The width of one UART bit in number of samples.
+ self.bit_width = float(self.samplerate) / float(self.options['baudrate'])
# Return true if we reached the middle of the desired bit, false otherwise.
def reached_bit(self, rxtx, bitnum):
# The startbit must be 0. If not, we report an error.
if self.startbit[rxtx] != 0:
- self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
- ['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
+ self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
# TODO: Abort? Ignore rest of the frame?
self.cur_data_bit[rxtx] = 0
self.state[rxtx] = 'GET DATA BITS'
- self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
- ['STARTBIT', rxtx, self.startbit[rxtx]])
- self.put(self.frame_start[rxtx], self.samplenum, self.out_ann,
- [ANN_ASCII, ['Start bit', 'Start', 'S']])
+ self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
+ self.putg([rxtx + 2, ['Start bit', 'Start', 'S']])
def get_data_bits(self, rxtx, signal):
# Skip samples until we're in the middle of the desired data bit.
if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1):
return
- # Save the sample number where the data byte starts.
+ # Save the sample number of the middle of the first data bit.
if self.startsample[rxtx] == -1:
self.startsample[rxtx] = self.samplenum
self.options['bit_order'])
# Return here, unless we already received all data bits.
- # TODO? Off-by-one?
if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1:
self.cur_data_bit[rxtx] += 1
return
self.state[rxtx] = 'GET PARITY BIT'
- self.put(self.startsample[rxtx], self.samplenum - 1, self.out_proto,
- ['DATA', rxtx, self.databyte[rxtx]])
+ self.putp(['DATA', rxtx, self.databyte[rxtx]])
+
+ b, f = self.databyte[rxtx], self.options['format']
+ if f == 'ascii':
+ c = chr(b) if b in range(30, 126 + 1) else '[%02X]' % b
+ self.putx(rxtx, [rxtx, [c]])
+ elif f == 'dec':
+ self.putx(rxtx, [rxtx, [str(b)]])
+ elif f == 'hex':
+ self.putx(rxtx, [rxtx, [hex(b)[2:].zfill(2).upper()]])
+ elif f == 'oct':
+ self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]])
+ elif f == 'bin':
+ self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]])
+ else:
+ raise Exception('Invalid data format option: %s' % f)
- s = 'RX: ' if (rxtx == RX) else 'TX: '
- self.putx(rxtx, [ANN_ASCII, [s + chr(self.databyte[rxtx])]])
- self.putx(rxtx, [ANN_DEC, [s + str(self.databyte[rxtx])]])
- self.putx(rxtx, [ANN_HEX, [s + hex(self.databyte[rxtx]),
- s + hex(self.databyte[rxtx])[2:]]])
- self.putx(rxtx, [ANN_OCT, [s + oct(self.databyte[rxtx]),
- s + oct(self.databyte[rxtx])[2:]]])
- self.putx(rxtx, [ANN_BITS, [s + bin(self.databyte[rxtx]),
- s + bin(self.databyte[rxtx])[2:]]])
+ self.putbin(rxtx, (rxtx, bytes([b])))
+ self.putbin(rxtx, (2, bytes([b])))
def get_parity_bit(self, rxtx, signal):
# If no parity is used/configured, skip to the next state immediately.
if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
self.databyte[rxtx], self.options['num_data_bits']):
- # TODO: Fix range.
- self.put(self.samplenum, self.samplenum, self.out_proto,
- ['PARITYBIT', rxtx, self.paritybit[rxtx]])
- self.put(self.samplenum, self.samplenum, self.out_ann,
- [ANN_ASCII, ['Parity bit', 'Parity', 'P']])
+ self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
+ self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']])
else:
- # TODO: Fix range.
# TODO: Return expected/actual parity values.
- self.put(self.samplenum, self.samplenum, self.out_proto,
- ['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
- self.put(self.samplenum, self.samplenum, self.out_ann,
- [ANN_ASCII, ['Parity error', 'Parity err', 'PE']])
+ self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
+ self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']])
# TODO: Currently only supports 1 stop bit.
def get_stop_bits(self, rxtx, signal):
# Stop bits must be 1. If not, we report an error.
if self.stopbit1[rxtx] != 1:
- self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
- ['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
+ self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
+ self.putg([rxtx + 8, ['Frame error', 'Frame err', 'FE']])
# TODO: Abort? Ignore the frame? Other?
self.state[rxtx] = 'WAIT FOR START BIT'
- # TODO: Fix range.
- self.put(self.samplenum, self.samplenum, self.out_proto,
- ['STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.put(self.samplenum, self.samplenum, self.out_ann,
- [ANN_ASCII, ['Stop bit', 'Stop', 'P']])
+ self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
+ self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']])
def decode(self, ss, es, data):
- # TODO: Either RX or TX could be omitted (optional probe).
+ if self.samplerate is None:
+ raise Exception("Cannot decode without samplerate.")
for (self.samplenum, pins) in data:
# Note: Ignoring identical samples here for performance reasons
# continue
self.oldpins, (rx, tx) = pins, pins
- # First sample: Save RX/TX value.
- if self.oldbit[RX] == None:
- self.oldbit[RX] = rx
- continue
- if self.oldbit[TX] == None:
- self.oldbit[TX] = tx
- continue
+ # Either RX or TX (but not both) can be omitted.
+ has_pin = [rx in (0, 1), tx in (0, 1)]
+ if has_pin == [False, False]:
+ raise Exception('Either TX or RX (or both) pins required.')
# State machine.
for rxtx in (RX, TX):
+ # Don't try to handle RX (or TX) if not supplied.
+ if not has_pin[rxtx]:
+ continue
+
signal = rx if (rxtx == RX) else tx
if self.state[rxtx] == 'WAIT FOR START BIT':