2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 # I2C protocol decoder
26 # The Inter-Integrated Circuit (I2C) bus is a bidirectional, multi-master
27 # bus using two signals (SCL = serial clock line, SDA = serial data line).
29 # There can be many devices on the same bus. Each device can potentially be
30 # master or slave (and that can change during runtime). Both slave and master
31 # can potentially play the transmitter or receiver role (this can also
34 # Possible maximum data rates:
35 # - Standard mode: 100 kbit/s
36 # - Fast mode: 400 kbit/s
37 # - Fast-mode Plus: 1 Mbit/s
38 # - High-speed mode: 3.4 Mbit/s
40 # START condition (S): SDA = falling, SCL = high
41 # Repeated START condition (Sr): same as S
42 # STOP condition (P): SDA = rising, SCL = high
44 # All data bytes on SDA are exactly 8 bits long (transmitted MSB-first).
45 # Each byte has to be followed by a 9th ACK/NACK bit. If that bit is low,
46 # that indicates an ACK, if it's high that indicates a NACK.
48 # After the first START condition, a master sends the device address of the
49 # slave it wants to talk to. Slave addresses are 7 bits long (MSB-first).
50 # After those 7 bits, a data direction bit is sent. If the bit is low that
51 # indicates a WRITE operation, if it's high that indicates a READ operation.
53 # Later an optional 10bit slave addressing scheme was added.
56 # http://www.nxp.com/acrobat/literature/9398/39340011.pdf (v2.1 spec)
57 # http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf (v3 spec)
58 # http://en.wikipedia.org/wiki/I2C
61 # TODO: Look into arbitration, collision detection, clock synchronisation, etc.
62 # TODO: Handle clock stretching.
63 # TODO: Handle combined messages / repeated START.
64 # TODO: Implement support for 7bit and 10bit slave addresses.
65 # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
66 # TODO: Implement support for detecting various bus errors.
68 # TODO: Return two buffers, one with structured data for the GUI to parse
69 # and display, and one with human-readable ASCII output.
72 """I2C protocol decoder"""
74 # FIXME: This should be passed in as metadata, not hardcoded here.
80 IDLE, START, ADDRESS, DATA = range(4)
83 # Get the bit number (and thus probe index) of the SCL/SDA signals.
84 scl_bit, sda_bit = signals
86 # Get SCL/SDA bit values (0/1 for low/high) of the first sample.
88 oldscl = (s & (1 << scl_bit)) >> scl_bit
89 oldsda = (s & (1 << sda_bit)) >> sda_bit
91 # Loop over all samples.
92 # TODO: Handle LAs with more/less than 8 channels.
93 for samplenum, s in enumerate(inbuf[1:]): # We skip the first byte...
97 # Get SCL/SDA bit values (0/1 for low/high).
98 scl = (s & (1 << scl_bit)) >> scl_bit
99 sda = (s & (1 << sda_bit)) >> sda_bit
101 # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
103 # START condition (S): SDA = falling, SCL = high
104 if (oldsda == 1 and sda == 0) and scl == 1:
105 o += "%d\t\tSTART\n" % samplenum
109 # Data latching by transmitter: SCL = low
113 # Data sampling of receiver: SCL = rising
114 elif (oldscl == 0 and scl == 1):
117 # o += "%d\t\tRECEIVED BIT %d: %d\n" % \
118 # (samplenum, 8 - bitcount, sda)
120 # Address and data are transmitted MSB-first.
127 # We received 8 address/data bits and the ACK/NACK bit.
128 data >>= 1 # Shift out unwanted ACK/NACK bit here.
129 # o += "%d\t\t%s: " % (samplenum, state)
130 o += "%d\t\tTODO:STATE: " % samplenum
131 ack = (sda == 1) and 'NACK' or 'ACK'
132 d = (state == ADDRESS) and (data & 0xfe) or data
135 wr = (data & 1) and ' (W)' or ' (R)'
137 o += "0x%02x%s (%s)\n" % (d, wr, ack)
140 # STOP condition (P): SDA = rising, SCL = high
141 elif (oldsda == 0 and sda == 1) and scl == 1:
142 o += "%d\t\tSTOP\n" % samplenum
145 # Save current SDA/SCL values for the next round.
151 # This is just a draft.
156 'desc': 'Inter-Integrated Circuit (I2C) bus',
158 'inputformats': ['raw'],
160 'SCL': 'Serial clock line',
161 'SDA': 'Serial data line',
163 'outputformats': ['i2c', 'ascii'],
166 # Use psyco (if available) as it results in huge performance improvements.