2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 # USB signalling (low-speed and full-speed) protocol decoder
24 import sigrokdecode as srd
27 Protocol output format:
40 - 'J', 'K', 'SE0', or 'SE1'
44 - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'.
47 # Low-/full-speed symbols.
48 # Note: Low-speed J and K are inverted compared to the full-speed J and K!
51 # (<dp>, <dm>): <symbol/state>
58 # (<dp>, <dm>): <symbol/state>
67 'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
68 'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
71 class Decoder(srd.Decoder):
74 name = 'USB signalling'
75 longname = 'Universal Serial Bus (LS/FS) signalling'
76 desc = 'USB (low-speed and full-speed) signalling protocol.'
79 outputs = ['usb_signalling']
81 {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
82 {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
86 'signalling': ['Signalling', 'full-speed'],
90 ['sop', 'Start of packet (SOP)'],
91 ['eop', 'End of packet (EOP)'],
93 ['stuffbit', 'Stuff bit'],
97 self.oldsym = 'J' # The "idle" state is J.
105 self.samplenum_target = None
107 self.consecutive_ones = 0
110 def start(self, metadata):
111 self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb_signalling')
112 self.out_ann = self.add(srd.OUTPUT_ANN, 'usb_signalling')
113 self.bitrate = bitrates[self.options['signalling']]
114 self.bitwidth = float(metadata['samplerate']) / float(self.bitrate)
115 self.halfbit = int(self.bitwidth / 2)
120 def putpx(self, data):
121 self.put(self.samplenum, self.samplenum, self.out_proto, data)
123 def putx(self, data):
124 self.put(self.samplenum, self.samplenum, self.out_ann, data)
126 def putpm(self, data):
127 s, h = self.samplenum, self.halfbit
128 self.put(self.ss_block - h, s + h, self.out_proto, data)
130 def putm(self, data):
131 s, h = self.samplenum, self.halfbit
132 self.put(self.ss_block - h, s + h, self.out_ann, data)
134 def putpb(self, data):
135 s, h = self.samplenum, self.halfbit
136 self.put(s - h, s + h, self.out_proto, data)
138 def putb(self, data):
139 s, h = self.samplenum, self.halfbit
140 self.put(s - h, s + h, self.out_ann, data)
142 def set_new_target_samplenum(self):
143 bitpos = self.ss_sop + (self.bitwidth / 2)
144 bitpos += self.bitnum * self.bitwidth
145 self.samplenum_target = int(bitpos)
147 def wait_for_sop(self, sym):
148 # Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
152 self.ss_sop = self.samplenum
153 self.set_new_target_samplenum()
154 self.putpx(['SOP', None])
155 self.putx([1, ['SOP']])
156 self.state = 'GET BIT'
158 def handle_bit(self, sym, b):
159 if self.consecutive_ones == 6 and b == '0':
161 self.putpb(['STUFF BIT', None])
162 self.putb([4, ['SB: %s/%s' % (sym, b)]])
163 self.consecutive_ones = 0
165 # Normal bit (not a stuff bit).
166 self.putpb(['BIT', b])
167 self.putb([3, ['%s/%s' % (sym, b)]])
169 self.consecutive_ones += 1
171 self.consecutive_ones = 0
173 def get_eop(self, sym):
174 # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
175 self.syms.append(sym)
176 self.putpb(['SYM', sym])
177 self.putb([0, ['%s' % sym]])
179 self.set_new_target_samplenum()
181 if self.syms[-2:] == ['SE0', 'J']:
183 self.putpm(['EOP', None])
184 self.putm([2, ['EOP']])
185 self.bitnum, self.syms, self.state = 0, [], 'IDLE'
186 self.consecutive_ones = 0
188 def get_bit(self, sym):
190 # Start of an EOP. Change state, run get_eop() for this bit.
191 self.state = 'GET EOP'
192 self.ss_block = self.samplenum
195 self.syms.append(sym)
196 self.putpb(['SYM', sym])
197 b = '0' if self.oldsym != sym else '1'
198 self.handle_bit(sym, b)
200 self.set_new_target_samplenum()
203 def decode(self, ss, es, data):
204 for (self.samplenum, pins) in data:
206 if self.state == 'IDLE':
207 # Ignore identical samples early on (for performance reasons).
208 if self.oldpins == pins:
211 sym = symbols[self.options['signalling']][tuple(pins)]
212 self.wait_for_sop(sym)
213 elif self.state in ('GET BIT', 'GET EOP'):
214 # Wait until we're in the middle of the desired bit.
215 if self.samplenum < self.samplenum_target:
217 sym = symbols[self.options['signalling']][tuple(pins)]
218 if self.state == 'GET BIT':
220 elif self.state == 'GET EOP':
223 raise Exception('Invalid state: %s' % self.state)