2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2011 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 # UART protocol decoder
26 # Universal Asynchronous Receiver Transmitter (UART) is a simple serial
27 # communication protocol which allows two devices to talk to each other.
29 # It uses just two data signals and a ground (GND) signal:
30 # - RX/RXD: Receive signal
31 # - TX/TXD: Transmit signal
33 # The protocol is asynchronous, i.e., there is no dedicated clock signal.
34 # Rather, both devices have to agree on a baudrate (number of bits to be
35 # transmitted per second) beforehand. Baudrates can be arbitrary in theory,
36 # but usually the choice is limited by the hardware UARTs that are used.
37 # Common values are 9600 or 115200.
39 # The protocol allows full-duplex transmission, i.e. both devices can send
40 # data at the same time. However, unlike SPI (which is always full-duplex,
41 # i.e., each send operation is automatically also a receive operation), UART
42 # allows one-way communication, too. In such a case only one signal (and GND)
45 # The data is sent over the TX line in so-called 'frames', which consist of:
46 # - Exactly one start bit (always 0/low).
47 # - Between 5 and 9 data bits.
48 # - An (optional) parity bit.
49 # - One or more stop bit(s).
51 # The idle state of the RX/TX line is 1/high. As the start bit is 0/low, the
52 # receiver can continually monitor its RX line for a falling edge, in order
53 # to detect the start bit.
55 # Once detected, it can (due to the agreed-upon baudrate and thus the known
56 # width/duration of one UART bit) sample the state of the RX line "in the
57 # middle" of each (start/data/parity/stop) bit it wants to analyze.
59 # It is configurable whether there is a parity bit in a frame, and if yes,
60 # which type of parity is used:
61 # - None: No parity bit is included.
62 # - Odd: The number of 1 bits in the data (and parity bit itself) is odd.
63 # - Even: The number of 1 bits in the data (and parity bit itself) is even.
64 # - Mark/one: The parity bit is always 1/high (also called 'mark state').
65 # - Space/zero: The parity bit is always 0/low (also called 'space state').
67 # It is also configurable how many stop bits are to be used:
68 # - 1 stop bit (most common case)
70 # - 1.5 stop bits (i.e., one stop bit, but 1.5 times the UART bit width)
71 # - 0.5 stop bits (i.e., one stop bit, but 0.5 times the UART bit width)
73 # The bit order of the 5-9 data bits is LSB-first.
75 # Possible special cases:
76 # - One or both data lines could be inverted, which also means that the idle
77 # state of the signal line(s) is low instead of high.
78 # - Only the data bits on one or both data lines (and the parity bit) could
79 # be inverted (but the start/stop bits remain non-inverted).
80 # - The bit order could be MSB-first instead of LSB-first.
81 # - The baudrate could change in the middle of the communication. This only
82 # happens in very special cases, and can only work if both devices know
83 # to which baudrate they are to switch, and when.
84 # - Theoretically, the baudrate on RX and the one on TX could also be
85 # different, but that's a very obscure case and probably doesn't happen
86 # very often in practice.
89 # - If there is a parity bit, but it doesn't match the expected parity,
90 # this is called a 'parity error'.
91 # - If there are no stop bit(s), that's called a 'frame error'.
100 WAIT_FOR_START_BIT = 0
123 # Output data formats
124 DATA_FORMAT_ASCII = 0
127 # TODO: Remove me later.
130 # Given a parity type to check (odd, even, zero, one), the value of the
131 # parity bit, the value of the data, and the length of the data (5-9 bits,
132 # usually 8 bits) return True if the parity is correct, False otherwise.
133 # PARITY_NONE is _not_ allowed as value for 'parity_type'.
134 def parity_ok(parity_type, parity_bit, data, num_data_bits):
136 # Handle easy cases first (parity bit is always 1 or 0).
137 if parity_type == PARITY_ZERO:
138 return parity_bit == 0
139 elif parity_type == PARITY_ONE:
140 return parity_bit == 1
142 # Count number of 1 (high) bits in the data (and the parity bit itself!).
143 parity = bin(data).count('1') + parity_bit
145 # Check for odd/even parity.
146 if parity_type == PARITY_ODD:
147 return (parity % 2) == 1
148 elif parity_type == PARITY_EVEN:
149 return (parity % 2) == 0
151 raise Exception('Invalid parity type: %d' % parity_type)
153 class Decoder(sigrokdecode.Decoder):
156 longname = 'Universal Asynchronous Receiver/Transmitter (UART)'
157 desc = 'Universal Asynchronous Receiver/Transmitter (UART)'
159 author = 'Uwe Hermann'
160 email = 'uwe@hermann-uwe.de'
165 # Allow specifying only one of the signals, e.g. if only one data
166 # direction exists (or is relevant).
167 {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
168 {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
171 'baudrate': ['UART baud rate', 115200],
172 'num_data_bits': ['Data bits', 8], # Valid: 5-9.
173 'parity': ['Parity', PARITY_NONE],
174 'parity_check': ['Check parity', True],
175 'num_stop_bits': ['Stop bit(s)', STOP_BITS_1],
176 'bit_order': ['Bit order', LSB_FIRST],
177 'data_format': ['Output data format', DATA_FORMAT_ASCII],
178 # TODO: Options to invert the signal(s).
182 def __init__(self, **kwargs):
183 self.output_protocol = None
184 self.output_annotation = None
186 # Set defaults, can be overridden in 'start'.
187 self.baudrate = 115200
188 self.num_data_bits = 8
189 self.parity = PARITY_NONE
190 self.check_parity = True
191 self.num_stop_bits = 1
192 self.bit_order = LSB_FIRST
193 self.data_format = DATA_FORMAT_ASCII
196 self.frame_start = -1
198 self.cur_data_bit = 0
201 self.startsample = -1
204 self.staterx = WAIT_FOR_START_BIT
209 def start(self, metadata):
210 self.samplerate = metadata['samplerate']
211 # self.output_protocol = self.output_new(2)
212 self.output_annotation = self.output_new(1)
215 ### self.baudrate = metadata['baudrate']
216 ### self.num_data_bits = metadata['num_data_bits']
217 ### self.parity = metadata['parity']
218 ### self.parity_check = metadata['parity_check']
219 ### self.num_stop_bits = metadata['num_stop_bits']
220 ### self.bit_order = metadata['bit_order']
221 ### self.data_format = metadata['data_format']
223 # The width of one UART bit in number of samples.
224 self.bit_width = float(self.samplerate) / float(self.baudrate)
229 # Return true if we reached the middle of the desired bit, false otherwise.
230 def reached_bit(self, bitnum):
231 # bitpos is the samplenumber which is in the middle of the
232 # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit
233 # (if used) or the first stop bit, and so on).
234 bitpos = self.frame_start + (self.bit_width / 2.0)
235 bitpos += bitnum * self.bit_width
236 if self.samplenum >= bitpos:
240 def reached_bit_last(self, bitnum):
241 bitpos = self.frame_start + ((bitnum + 1) * self.bit_width)
242 if self.samplenum >= bitpos:
246 def wait_for_start_bit(self, old_signal, signal):
247 # The start bit is always 0 (low). As the idle UART (and the stop bit)
248 # level is 1 (high), the beginning of a start bit is a falling edge.
249 if not (old_signal == 1 and signal == 0):
252 # Save the sample number where the start bit begins.
253 self.frame_start = self.samplenum
255 self.staterx = GET_START_BIT
257 def get_start_bit(self, signal):
258 # Skip samples until we're in the middle of the start bit.
259 if not self.reached_bit(0):
262 self.startbit = signal
264 if self.startbit != 0:
265 # TODO: Startbit must be 0. If not, we report an error.
268 self.cur_data_bit = 0
270 self.startsample = -1
272 self.staterx = GET_DATA_BITS
274 if quick_hack: # TODO
277 o = [{'type': 'S', 'range': (self.frame_start, self.samplenum),
278 'data': None, 'ann': 'Start bit'}]
281 def get_data_bits(self, signal):
282 # Skip samples until we're in the middle of the desired data bit.
283 if not self.reached_bit(self.cur_data_bit + 1):
286 # Save the sample number where the data byte starts.
287 if self.startsample == -1:
288 self.startsample = self.samplenum
290 # Get the next data bit in LSB-first or MSB-first fashion.
291 if self.bit_order == LSB_FIRST:
293 self.databyte |= (signal << (self.num_data_bits - 1))
294 elif self.bit_order == MSB_FIRST:
296 self.databyte |= (signal << 0)
298 raise Exception('Invalid bit order value: %d', self.bit_order)
300 # Return here, unless we already received all data bits.
301 if self.cur_data_bit < self.num_data_bits - 1: # TODO? Off-by-one?
302 self.cur_data_bit += 1
305 # Convert the data byte into the configured format.
306 if self.data_format == DATA_FORMAT_ASCII:
307 d = chr(self.databyte)
308 elif self.data_format == DATA_FORMAT_HEX:
309 d = '0x%02x' % self.databyte
311 raise Exception('Invalid data format value: %d', self.data_format)
313 self.staterx = GET_PARITY_BIT
315 if quick_hack: # TODO
318 o = [{'type': 'D', 'range': (self.startsample, self.samplenum - 1),
319 'data': d, 'ann': None}]
323 def get_parity_bit(self, signal):
324 # If no parity is used/configured, skip to the next state immediately.
325 if self.parity == PARITY_NONE:
326 self.staterx = GET_STOP_BITS
329 # Skip samples until we're in the middle of the parity bit.
330 if not self.reached_bit(self.num_data_bits + 1):
333 self.paritybit = signal
335 self.staterx = GET_STOP_BITS
337 if parity_ok(self.parity, self.paritybit, self.databyte,
339 if quick_hack: # TODO
343 o = [{'type': 'P', 'range': (self.samplenum, self.samplenum),
344 'data': self.paritybit, 'ann': 'Parity bit'}]
346 if quick_hack: # TODO
348 o = [{'type': 'PE', 'range': (self.samplenum, self.samplenum),
349 'data': self.paritybit, 'ann': 'Parity error'}]
353 # TODO: Currently only supports 1 stop bit.
354 def get_stop_bits(self, signal):
355 # Skip samples until we're in the middle of the stop bit(s).
356 skip_parity = 0 if self.parity == PARITY_NONE else 1
357 if not self.reached_bit(self.num_data_bits + 1 + skip_parity):
360 self.stopbit1 = signal
362 if self.stopbit1 != 1:
363 # TODO: Stop bits must be 1. If not, we report an error.
366 self.staterx = WAIT_FOR_START_BIT
368 if quick_hack: # TODO
372 o = [{'type': 'P', 'range': (self.samplenum, self.samplenum),
373 'data': None, 'ann': 'Stop bit'}]
376 def decode(self, timeoffset, duration, data): # TODO
379 # for (samplenum, (rx, tx)) in data:
380 for (samplenum, (rx,)) in data:
382 # TODO: Start counting at 0 or 1? Increase before or after?
385 # First sample: Save RX/TX value.
386 if self.oldrx == None:
387 # Get RX/TX bit values (0/1 for low/high) of the first sample.
393 if self.staterx == WAIT_FOR_START_BIT:
394 self.wait_for_start_bit(self.oldrx, rx)
395 elif self.staterx == GET_START_BIT:
396 out += self.get_start_bit(rx)
397 elif self.staterx == GET_DATA_BITS:
398 out += self.get_data_bits(rx)
399 elif self.staterx == GET_PARITY_BIT:
400 out += self.get_parity_bit(rx)
401 elif self.staterx == GET_STOP_BITS:
402 out += self.get_stop_bits(rx)
404 raise Exception('Invalid state: %s' % self.staterx)
406 # Save current RX/TX values for the next round.
411 # self.put(0, 0, self.output_protocol, out_proto)
412 self.put(0, 0, self.output_annotation, out)