2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 # UART protocol decoder
26 # Universal Asynchronous Receiver Transmitter (UART) is a simple serial
27 # communication protocol which allows two devices to talk to each other.
29 # It uses just two data signals and a ground (GND) signal:
30 # - RX/RXD: Receive signal
31 # - TX/TXD: Transmit signal
33 # The protocol is asynchronous, i.e., there is no dedicated clock signal.
34 # Rather, both devices have to agree on a baudrate (number of bits to be
35 # transmitted per second) beforehand. Baudrates can be arbitrary in theory,
36 # but usually the choice is limited by the hardware UARTs that are used.
37 # Common values are 9600 or 115200.
39 # The protocol allows full-duplex transmission, i.e. both devices can send
40 # data at the same time. However, unlike SPI (which is always full-duplex,
41 # i.e., each send operation is automatically also a receive operation), UART
42 # allows one-way communication, too. In such a case only one signal (and GND)
45 # The data is sent over the TX line in so-called 'frames', which consist of:
46 # - Exactly one start bit (always 0/low).
47 # - Between 5 and 9 data bits.
48 # - An (optional) parity bit.
49 # - One or more stop bit(s).
51 # The idle state of the RX/TX line is 1/high. As the start bit is 0/low, the
52 # receiver can continually monitor its RX line for a falling edge, in order
53 # to detect the start bit.
55 # Once detected, it can (due to the agreed-upon baudrate and thus the known
56 # width/duration of one UART bit) sample the state of the RX line "in the
57 # middle" of each (start/data/parity/stop) bit it wants to analyze.
59 # It is configurable whether there is a parity bit in a frame, and if yes,
60 # which type of parity is used:
61 # - None: No parity bit is included.
62 # - Odd: The number of 1 bits in the data (and parity bit itself) is odd.
63 # - Even: The number of 1 bits in the data (and parity bit itself) is even.
64 # - Mark/one: The parity bit is always 1/high (also called 'mark state').
65 # - Space/zero: The parity bit is always 0/low (also called 'space state').
67 # It is also configurable how many stop bits are to be used:
68 # - 1 stop bit (most common case)
70 # - 1.5 stop bits (i.e., one stop bit, but 1.5 times the UART bit width)
71 # - 0.5 stop bits (i.e., one stop bit, but 0.5 times the UART bit width)
73 # The bit order of the 5-9 data bits is LSB-first.
75 # Possible special cases:
76 # - One or both data lines could be inverted, which also means that the idle
77 # state of the signal line(s) is low instead of high.
78 # - Only the data bits on one or both data lines (and the parity bit) could
79 # be inverted (but the start/stop bits remain non-inverted).
80 # - The bit order could be MSB-first instead of LSB-first.
81 # - The baudrate could change in the middle of the communication. This only
82 # happens in very special cases, and can only work if both devices know
83 # to which baudrate they are to switch, and when.
84 # - Theoretically, the baudrate on RX and the one on TX could also be
85 # different, but that's a very obscure case and probably doesn't happen
86 # very often in practice.
89 # - If there is a parity bit, but it doesn't match the expected parity,
90 # this is called a 'parity error'.
91 # - If there are no stop bit(s), that's called a 'frame error'.
98 # Protocol output format:
101 # [<packet-type>, <rxtx>, <packet-data>]
103 # This is the list of <packet-types>s and their respective <packet-data>:
104 # - T_START: The data is the (integer) value of the start bit (0 or 1).
105 # - T_DATA: The data is the (integer) value of the UART data. Valid values
106 # range from 0 to 512 (as the data can be up to 9 bits in size).
107 # - T_PARITY: The data is the (integer) value of the parity bit (0 or 1).
108 # - T_STOP: The data is the (integer) value of the stop bit (0 or 1).
109 # - T_INVALID_START: The data is the (integer) value of the start bit (0 or 1).
110 # - T_INVALID_STOP: The data is the (integer) value of the stop bit (0 or 1).
111 # - T_PARITY_ERROR: The data is a tuple with two entries. The first one is
112 # the expected parity value, the second is the actual parity value.
114 # The <rxtx> field is 0 for RX packets, 1 for TX packets.
117 import sigrokdecode as srd
120 WAIT_FOR_START_BIT = 0
126 # Used for differentiating between the two data directions.
147 # Annotation feed formats
154 # Protocol output packet types
163 # Given a parity type to check (odd, even, zero, one), the value of the
164 # parity bit, the value of the data, and the length of the data (5-9 bits,
165 # usually 8 bits) return True if the parity is correct, False otherwise.
166 # PARITY_NONE is _not_ allowed as value for 'parity_type'.
167 def parity_ok(parity_type, parity_bit, data, num_data_bits):
169 # Handle easy cases first (parity bit is always 1 or 0).
170 if parity_type == PARITY_ZERO:
171 return parity_bit == 0
172 elif parity_type == PARITY_ONE:
173 return parity_bit == 1
175 # Count number of 1 (high) bits in the data (and the parity bit itself!).
176 parity = bin(data).count('1') + parity_bit
178 # Check for odd/even parity.
179 if parity_type == PARITY_ODD:
180 return (parity % 2) == 1
181 elif parity_type == PARITY_EVEN:
182 return (parity % 2) == 0
184 raise Exception('Invalid parity type: %d' % parity_type)
186 class Decoder(srd.Decoder):
190 longname = 'Universal Asynchronous Receiver/Transmitter'
191 desc = 'Universal Asynchronous Receiver/Transmitter (UART)'
197 # Allow specifying only one of the signals, e.g. if only one data
198 # direction exists (or is relevant).
199 {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
200 {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
203 'baudrate': ['Baud rate', 115200],
204 'num_data_bits': ['Data bits', 8], # Valid: 5-9.
205 'parity': ['Parity', PARITY_NONE], # TODO: Rename to parity_type.
206 'parity_check': ['Check parity', True], # TODO: Bool supported?
207 'num_stop_bits': ['Stop bit(s)', STOP_BITS_1],
208 'bit_order': ['Bit order', LSB_FIRST],
209 # TODO: Options to invert the signal(s).
212 ['ASCII', 'Data bytes as ASCII characters'],
213 ['Decimal', 'Databytes as decimal, integer values'],
214 ['Hex', 'Data bytes in hex format'],
215 ['Octal', 'Data bytes as octal numbers'],
216 ['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
219 def putx(self, rxtx, data):
220 self.put(self.startsample[rxtx], self.samplenum - 1, self.out_ann, data)
222 def __init__(self, **kwargs):
224 self.frame_start = [-1, -1]
225 self.startbit = [-1, -1]
226 self.cur_data_bit = [0, 0]
227 self.databyte = [0, 0]
228 self.stopbit1 = [-1, -1]
229 self.startsample = [-1, -1]
232 self.state = [WAIT_FOR_START_BIT, WAIT_FOR_START_BIT]
234 self.oldbit = [None, None]
236 def start(self, metadata):
237 self.samplerate = metadata['samplerate']
238 self.out_proto = self.add(srd.OUTPUT_PROTO, 'uart')
239 self.out_ann = self.add(srd.OUTPUT_ANN, 'uart')
241 # The width of one UART bit in number of samples.
243 float(self.samplerate) / float(self.options['baudrate'])
248 # Return true if we reached the middle of the desired bit, false otherwise.
249 def reached_bit(self, rxtx, bitnum):
250 # bitpos is the samplenumber which is in the middle of the
251 # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit
252 # (if used) or the first stop bit, and so on).
253 bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0)
254 bitpos += bitnum * self.bit_width
255 if self.samplenum >= bitpos:
259 def reached_bit_last(self, rxtx, bitnum):
260 bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width)
261 if self.samplenum >= bitpos:
265 def wait_for_start_bit(self, rxtx, old_signal, signal):
266 # The start bit is always 0 (low). As the idle UART (and the stop bit)
267 # level is 1 (high), the beginning of a start bit is a falling edge.
268 if not (old_signal == 1 and signal == 0):
271 # Save the sample number where the start bit begins.
272 self.frame_start[rxtx] = self.samplenum
274 self.state[rxtx] = GET_START_BIT
276 def get_start_bit(self, rxtx, signal):
277 # Skip samples until we're in the middle of the start bit.
278 if not self.reached_bit(rxtx, 0):
281 self.startbit[rxtx] = signal
283 # The startbit must be 0. If not, we report an error.
284 if self.startbit[rxtx] != 0:
285 self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
286 [T_INVALID_START, rxtx, self.startbit[rxtx]])
287 # TODO: Abort? Ignore rest of the frame?
289 self.cur_data_bit[rxtx] = 0
290 self.databyte[rxtx] = 0
291 self.startsample[rxtx] = -1
293 self.state[rxtx] = GET_DATA_BITS
295 self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
296 [T_START, rxtx, self.startbit[rxtx]])
297 self.put(self.frame_start[rxtx], self.samplenum, self.out_ann,
298 [ANN_ASCII, ['Start bit', 'Start', 'S']])
300 def get_data_bits(self, rxtx, signal):
301 # Skip samples until we're in the middle of the desired data bit.
302 if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1):
305 # Save the sample number where the data byte starts.
306 if self.startsample[rxtx] == -1:
307 self.startsample[rxtx] = self.samplenum
309 # Get the next data bit in LSB-first or MSB-first fashion.
310 if self.options['bit_order'] == LSB_FIRST:
311 self.databyte[rxtx] >>= 1
312 self.databyte[rxtx] |= (signal << (self.options['num_data_bits'] - 1))
313 elif self.options['bit_order'] == MSB_FIRST:
314 self.databyte[rxtx] <<= 1
315 self.databyte[rxtx] |= (signal << 0)
317 raise Exception('Invalid bit order value: %d',
318 self.options['bit_order'])
320 # Return here, unless we already received all data bits.
322 if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1:
323 self.cur_data_bit[rxtx] += 1
326 self.state[rxtx] = GET_PARITY_BIT
328 self.put(self.startsample[rxtx], self.samplenum - 1, self.out_proto,
329 [T_DATA, rxtx, self.databyte[rxtx]])
331 s = 'RX: ' if (rxtx == RX) else 'TX: '
332 self.putx(rxtx, [ANN_ASCII, [s + chr(self.databyte[rxtx])]])
333 self.putx(rxtx, [ANN_DEC, [s + str(self.databyte[rxtx])]])
334 self.putx(rxtx, [ANN_HEX, [s + hex(self.databyte[rxtx]),
335 s + hex(self.databyte[rxtx])[2:]]])
336 self.putx(rxtx, [ANN_OCT, [s + oct(self.databyte[rxtx]),
337 s + oct(self.databyte[rxtx])[2:]]])
338 self.putx(rxtx, [ANN_BITS, [s + bin(self.databyte[rxtx]),
339 s + bin(self.databyte[rxtx])[2:]]])
341 def get_parity_bit(self, rxtx, signal):
342 # If no parity is used/configured, skip to the next state immediately.
343 if self.options['parity'] == PARITY_NONE:
344 self.state[rxtx] = GET_STOP_BITS
347 # Skip samples until we're in the middle of the parity bit.
348 if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1):
351 self.paritybit[rxtx] = signal
353 self.state[rxtx] = GET_STOP_BITS
355 if parity_ok(self.options['parity'], self.paritybit[rxtx],
356 self.databyte[rxtx], self.options['num_data_bits']):
358 self.put(self.samplenum, self.samplenum, self.out_proto,
359 [T_PARITY_BIT, rxtx, self.paritybit[rxtx]])
360 self.put(self.samplenum, self.samplenum, self.out_ann,
361 [ANN_ASCII, ['Parity bit', 'Parity', 'P']])
364 # TODO: Return expected/actual parity values.
365 self.put(self.samplenum, self.samplenum, self.out_proto,
366 [T_PARITY_ERROR, rxtx, (0, 1)]) # FIXME: Dummy tuple...
367 self.put(self.samplenum, self.samplenum, self.out_ann,
368 [ANN_ASCII, ['Parity error', 'Parity err', 'PE']])
370 # TODO: Currently only supports 1 stop bit.
371 def get_stop_bits(self, rxtx, signal):
372 # Skip samples until we're in the middle of the stop bit(s).
373 skip_parity = 0 if self.options['parity'] == PARITY_NONE else 1
374 b = self.options['num_data_bits'] + 1 + skip_parity
375 if not self.reached_bit(rxtx, b):
378 self.stopbit1[rxtx] = signal
380 # Stop bits must be 1. If not, we report an error.
381 if self.stopbit1[rxtx] != 1:
382 self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
383 [T_INVALID_STOP, rxtx, self.stopbit1[rxtx]])
384 # TODO: Abort? Ignore the frame? Other?
386 self.state[rxtx] = WAIT_FOR_START_BIT
389 self.put(self.samplenum, self.samplenum, self.out_proto,
390 [T_STOP, rxtx, self.stopbit1[rxtx]])
391 self.put(self.samplenum, self.samplenum, self.out_ann,
392 [ANN_ASCII, ['Stop bit', 'Stop', 'P']])
394 def decode(self, ss, es, data): # TODO
395 for (samplenum, (rx, tx)) in data:
397 # TODO: Start counting at 0 or 1? Increase before or after?
400 # First sample: Save RX/TX value.
401 if self.oldbit[RX] == None:
404 if self.oldbit[TX] == None:
409 for rxtx in (RX, TX):
410 signal = rx if (rxtx == RX) else tx
412 if self.state[rxtx] == WAIT_FOR_START_BIT:
413 self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal)
414 elif self.state[rxtx] == GET_START_BIT:
415 self.get_start_bit(rxtx, signal)
416 elif self.state[rxtx] == GET_DATA_BITS:
417 self.get_data_bits(rxtx, signal)
418 elif self.state[rxtx] == GET_PARITY_BIT:
419 self.get_parity_bit(rxtx, signal)
420 elif self.state[rxtx] == GET_STOP_BITS:
421 self.get_stop_bits(rxtx, signal)
423 raise Exception('Invalid state: %s' % self.state[rxtx])
425 # Save current RX/TX values for the next round.
426 self.oldbit[rxtx] = signal