2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # UART protocol decoder
23 import sigrokdecode as srd
25 # Used for differentiating between the two data directions.
29 # Annotation feed formats
36 # Given a parity type to check (odd, even, zero, one), the value of the
37 # parity bit, the value of the data, and the length of the data (5-9 bits,
38 # usually 8 bits) return True if the parity is correct, False otherwise.
39 # 'none' is _not_ allowed as value for 'parity_type'.
40 def parity_ok(parity_type, parity_bit, data, num_data_bits):
42 # Handle easy cases first (parity bit is always 1 or 0).
43 if parity_type == 'zero':
44 return parity_bit == 0
45 elif parity_type == 'one':
46 return parity_bit == 1
48 # Count number of 1 (high) bits in the data (and the parity bit itself!).
49 ones = bin(data).count('1') + parity_bit
51 # Check for odd/even parity.
52 if parity_type == 'odd':
53 return (ones % 2) == 1
54 elif parity_type == 'even':
55 return (ones % 2) == 0
57 raise Exception('Invalid parity type: %d' % parity_type)
59 class Decoder(srd.Decoder):
63 longname = 'Universal Asynchronous Receiver/Transmitter'
64 desc = 'Asynchronous, serial bus.'
69 # Allow specifying only one of the signals, e.g. if only one data
70 # direction exists (or is relevant).
71 {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
72 {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
76 'baudrate': ['Baud rate', 115200],
77 'num_data_bits': ['Data bits', 8], # Valid: 5-9.
78 'parity_type': ['Parity type', 'none'],
79 'parity_check': ['Check parity?', 'yes'], # TODO: Bool supported?
80 'num_stop_bits': ['Stop bit(s)', '1'], # String! 0, 0.5, 1, 1.5.
81 'bit_order': ['Bit order', 'lsb-first'],
82 # TODO: Options to invert the signal(s).
85 ['ASCII', 'Data bytes as ASCII characters'],
86 ['Decimal', 'Databytes as decimal, integer values'],
87 ['Hex', 'Data bytes in hex format'],
88 ['Octal', 'Data bytes as octal numbers'],
89 ['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
92 def putx(self, rxtx, data):
93 self.put(self.startsample[rxtx], self.samplenum - 1, self.out_ann, data)
95 def __init__(self, **kwargs):
97 self.frame_start = [-1, -1]
98 self.startbit = [-1, -1]
99 self.cur_data_bit = [0, 0]
100 self.databyte = [0, 0]
101 self.paritybit = [-1, -1]
102 self.stopbit1 = [-1, -1]
103 self.startsample = [-1, -1]
104 self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
105 self.oldbit = [None, None]
108 def start(self, metadata):
109 self.samplerate = metadata['samplerate']
110 self.out_proto = self.add(srd.OUTPUT_PROTO, 'uart')
111 self.out_ann = self.add(srd.OUTPUT_ANN, 'uart')
113 # The width of one UART bit in number of samples.
115 float(self.samplerate) / float(self.options['baudrate'])
120 # Return true if we reached the middle of the desired bit, false otherwise.
121 def reached_bit(self, rxtx, bitnum):
122 # bitpos is the samplenumber which is in the middle of the
123 # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit
124 # (if used) or the first stop bit, and so on).
125 bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0)
126 bitpos += bitnum * self.bit_width
127 if self.samplenum >= bitpos:
131 def reached_bit_last(self, rxtx, bitnum):
132 bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width)
133 if self.samplenum >= bitpos:
137 def wait_for_start_bit(self, rxtx, old_signal, signal):
138 # The start bit is always 0 (low). As the idle UART (and the stop bit)
139 # level is 1 (high), the beginning of a start bit is a falling edge.
140 if not (old_signal == 1 and signal == 0):
143 # Save the sample number where the start bit begins.
144 self.frame_start[rxtx] = self.samplenum
146 self.state[rxtx] = 'GET START BIT'
148 def get_start_bit(self, rxtx, signal):
149 # Skip samples until we're in the middle of the start bit.
150 if not self.reached_bit(rxtx, 0):
153 self.startbit[rxtx] = signal
155 # The startbit must be 0. If not, we report an error.
156 if self.startbit[rxtx] != 0:
157 self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
158 ['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
159 # TODO: Abort? Ignore rest of the frame?
161 self.cur_data_bit[rxtx] = 0
162 self.databyte[rxtx] = 0
163 self.startsample[rxtx] = -1
165 self.state[rxtx] = 'GET DATA BITS'
167 self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
168 ['STARTBIT', rxtx, self.startbit[rxtx]])
169 self.put(self.frame_start[rxtx], self.samplenum, self.out_ann,
170 [ANN_ASCII, ['Start bit', 'Start', 'S']])
172 def get_data_bits(self, rxtx, signal):
173 # Skip samples until we're in the middle of the desired data bit.
174 if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1):
177 # Save the sample number where the data byte starts.
178 if self.startsample[rxtx] == -1:
179 self.startsample[rxtx] = self.samplenum
181 # Get the next data bit in LSB-first or MSB-first fashion.
182 if self.options['bit_order'] == 'lsb-first':
183 self.databyte[rxtx] >>= 1
184 self.databyte[rxtx] |= \
185 (signal << (self.options['num_data_bits'] - 1))
186 elif self.options['bit_order'] == 'msb-first':
187 self.databyte[rxtx] <<= 1
188 self.databyte[rxtx] |= (signal << 0)
190 raise Exception('Invalid bit order value: %s',
191 self.options['bit_order'])
193 # Return here, unless we already received all data bits.
195 if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1:
196 self.cur_data_bit[rxtx] += 1
199 self.state[rxtx] = 'GET PARITY BIT'
201 self.put(self.startsample[rxtx], self.samplenum - 1, self.out_proto,
202 ['DATA', rxtx, self.databyte[rxtx]])
204 s = 'RX: ' if (rxtx == RX) else 'TX: '
205 self.putx(rxtx, [ANN_ASCII, [s + chr(self.databyte[rxtx])]])
206 self.putx(rxtx, [ANN_DEC, [s + str(self.databyte[rxtx])]])
207 self.putx(rxtx, [ANN_HEX, [s + hex(self.databyte[rxtx]),
208 s + hex(self.databyte[rxtx])[2:]]])
209 self.putx(rxtx, [ANN_OCT, [s + oct(self.databyte[rxtx]),
210 s + oct(self.databyte[rxtx])[2:]]])
211 self.putx(rxtx, [ANN_BITS, [s + bin(self.databyte[rxtx]),
212 s + bin(self.databyte[rxtx])[2:]]])
214 def get_parity_bit(self, rxtx, signal):
215 # If no parity is used/configured, skip to the next state immediately.
216 if self.options['parity_type'] == 'none':
217 self.state[rxtx] = 'GET STOP BITS'
220 # Skip samples until we're in the middle of the parity bit.
221 if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1):
224 self.paritybit[rxtx] = signal
226 self.state[rxtx] = 'GET STOP BITS'
228 if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
229 self.databyte[rxtx], self.options['num_data_bits']):
231 self.put(self.samplenum, self.samplenum, self.out_proto,
232 ['PARITYBIT', rxtx, self.paritybit[rxtx]])
233 self.put(self.samplenum, self.samplenum, self.out_ann,
234 [ANN_ASCII, ['Parity bit', 'Parity', 'P']])
237 # TODO: Return expected/actual parity values.
238 self.put(self.samplenum, self.samplenum, self.out_proto,
239 ['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
240 self.put(self.samplenum, self.samplenum, self.out_ann,
241 [ANN_ASCII, ['Parity error', 'Parity err', 'PE']])
243 # TODO: Currently only supports 1 stop bit.
244 def get_stop_bits(self, rxtx, signal):
245 # Skip samples until we're in the middle of the stop bit(s).
246 skip_parity = 0 if self.options['parity_type'] == 'none' else 1
247 b = self.options['num_data_bits'] + 1 + skip_parity
248 if not self.reached_bit(rxtx, b):
251 self.stopbit1[rxtx] = signal
253 # Stop bits must be 1. If not, we report an error.
254 if self.stopbit1[rxtx] != 1:
255 self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
256 ['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
257 # TODO: Abort? Ignore the frame? Other?
259 self.state[rxtx] = 'WAIT FOR START BIT'
262 self.put(self.samplenum, self.samplenum, self.out_proto,
263 ['STOPBIT', rxtx, self.stopbit1[rxtx]])
264 self.put(self.samplenum, self.samplenum, self.out_ann,
265 [ANN_ASCII, ['Stop bit', 'Stop', 'P']])
267 def decode(self, ss, es, data):
268 # TODO: Either RX or TX could be omitted (optional probe).
269 for (self.samplenum, pins) in data:
271 # Note: Ignoring identical samples here for performance reasons
272 # is not possible for this PD, at least not in the current state.
273 # if self.oldpins == pins:
275 self.oldpins, (rx, tx) = pins, pins
277 # First sample: Save RX/TX value.
278 if self.oldbit[RX] == None:
281 if self.oldbit[TX] == None:
286 for rxtx in (RX, TX):
287 signal = rx if (rxtx == RX) else tx
289 if self.state[rxtx] == 'WAIT FOR START BIT':
290 self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal)
291 elif self.state[rxtx] == 'GET START BIT':
292 self.get_start_bit(rxtx, signal)
293 elif self.state[rxtx] == 'GET DATA BITS':
294 self.get_data_bits(rxtx, signal)
295 elif self.state[rxtx] == 'GET PARITY BIT':
296 self.get_parity_bit(rxtx, signal)
297 elif self.state[rxtx] == 'GET STOP BITS':
298 self.get_stop_bits(rxtx, signal)
300 raise Exception('Invalid state: %d' % self.state[rxtx])
302 # Save current RX/TX values for the next round.
303 self.oldbit[rxtx] = signal