2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # Texas Instruments TLC5620 protocol decoder
23 import sigrokdecode as srd
32 class Decoder(srd.Decoder):
36 longname = 'Texas Instruments TLC5620'
37 desc = 'Texas Instruments TLC5620 8-bit quad DAC.'
42 {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'},
43 {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'},
46 {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'},
47 {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'},
51 ['Text', 'Human-readable text'],
52 ['Warnings', 'Human-readable warnings'],
55 def __init__(self, **kwargs):
56 self.oldpins = self.oldclk = self.oldload = self.oldldac = None
59 self.ss_dac = self.es_dac = 0
60 self.ss_gain = self.es_gain = 0
61 self.ss_value = self.es_value = 0
62 self.dac_select = self.gain = self.dac_value = None
64 def start(self, metadata):
65 # self.out_proto = self.add(srd.OUTPUT_PROTO, 'tlc5620')
66 self.out_ann = self.add(srd.OUTPUT_ANN, 'tlc5620')
71 def handle_11bits(self):
72 s = "".join(str(i) for i in self.bits[:2])
73 self.dac_select = dacs[int(s, 2)]
74 self.put(self.ss_dac, self.es_dac, self.out_ann,
75 [0, ['DAC select: %s' % self.dac_select]])
77 self.gain = 1 + self.bits[2]
78 self.put(self.ss_gain, self.es_gain, self.out_ann,
79 [0, ['Gain: x%d' % self.gain]])
81 s = "".join(str(i) for i in self.bits[3:])
82 self.dac_value = int(s, 2)
83 self.put(self.ss_value, self.es_value, self.out_ann,
84 [0, ['DAC value: %d' % self.dac_value]])
86 def handle_falling_edge_load(self):
87 self.put(self.samplenum, self.samplenum, self.out_ann,
88 [0, ['Setting %s value to %d (x%d gain)' % \
89 (self.dac_select, self.dac_value, self.gain)]])
91 def handle_falling_edge_ldac(self):
92 self.put(self.samplenum, self.samplenum, self.out_ann,
93 [0, ['Falling edge on LDAC pin']])
95 def handle_new_dac_bit(self):
96 self.bits.append(self.datapin)
98 # Wait until we have read 11 bits, then parse them.
99 l, s = len(self.bits), self.samplenum
103 self.es_dac = self.ss_gain = s
105 self.es_gain = self.ss_value = s
111 def decode(self, ss, es, data):
112 for (self.samplenum, pins) in data:
114 # Ignore identical samples early on (for performance reasons).
115 if self.oldpins == pins:
117 self.oldpins, (clk, self.datapin, load, ldac) = pins, pins
119 # DATA is shifted in the DAC on the falling CLK edge (MSB-first).
120 # A falling edge of LOAD will latch the data.
122 if self.oldload == 1 and load == 0:
123 self.handle_falling_edge_load()
124 if self.oldldac == 1 and ldac == 0:
125 self.handle_falling_edge_ldac()
126 if self.oldclk == 1 and clk == 0:
127 self.handle_new_dac_bit()