2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
30 class Decoder(srd.Decoder):
34 longname = 'Texas Instruments TLC5620'
35 desc = 'Texas Instruments TLC5620 8-bit quad DAC.'
40 {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'},
41 {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'},
44 {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'},
45 {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'},
49 ['dac-select', 'DAC select'],
51 ['value', 'DAC value'],
52 ['data-latch', 'Data latch point'],
53 ['ldac-fall', 'LDAC falling edge'],
56 def __init__(self, **kwargs):
57 self.oldpins = self.oldclk = self.oldload = self.oldldac = None
60 self.ss_dac = self.es_dac = 0
61 self.ss_gain = self.es_gain = 0
62 self.ss_value = self.es_value = 0
63 self.dac_select = self.gain = self.dac_value = None
66 # self.out_python = self.register(srd.OUTPUT_PYTHON)
67 self.out_ann = self.register(srd.OUTPUT_ANN)
69 def handle_11bits(self):
70 s = "".join(str(i) for i in self.bits[:2])
71 self.dac_select = s = dacs[int(s, 2)]
72 self.put(self.ss_dac, self.es_dac, self.out_ann,
73 [0, ['DAC select: %s' % s, 'DAC sel: %s' % s,
74 'DAC: %s' % s, 'D: %s' % s, s, s[3]]])
76 self.gain = g = 1 + self.bits[2]
77 self.put(self.ss_gain, self.es_gain, self.out_ann,
78 [1, ['Gain: x%d' % g, 'G: x%d' % g, 'x%d' % g]])
80 s = "".join(str(i) for i in self.bits[3:])
81 self.dac_value = v = int(s, 2)
82 self.put(self.ss_value, self.es_value, self.out_ann,
83 [2, ['DAC value: %d' % v, 'Value: %d' % v, 'Val: %d' % v,
84 'V: %d' % v, '%d' % v]])
86 def handle_falling_edge_load(self):
87 s, v, g = self.dac_select, self.dac_value, self.gain
88 self.put(self.samplenum, self.samplenum, self.out_ann,
89 [3, ['Setting %s value to %d (x%d gain)' % (s, v, g),
90 '%s=%d (x%d gain)' % (s, v, g)]])
92 def handle_falling_edge_ldac(self):
93 self.put(self.samplenum, self.samplenum, self.out_ann,
94 [4, ['Falling edge on LDAC pin', 'LDAC fall', 'LDAC']])
96 def handle_new_dac_bit(self):
97 self.bits.append(self.datapin)
99 # Wait until we have read 11 bits, then parse them.
100 l, s = len(self.bits), self.samplenum
104 self.es_dac = self.ss_gain = s
106 self.es_gain = self.ss_value = s
112 def decode(self, ss, es, data):
113 for (self.samplenum, pins) in data:
115 # Ignore identical samples early on (for performance reasons).
116 if self.oldpins == pins:
118 self.oldpins, (clk, self.datapin, load, ldac) = pins, pins
120 # DATA is shifted in the DAC on the falling CLK edge (MSB-first).
121 # A falling edge of LOAD will latch the data.
123 if self.oldload == 1 and load == 0:
124 self.handle_falling_edge_load()
125 if self.oldldac == 1 and ldac == 0:
126 self.handle_falling_edge_ldac()
127 if self.oldclk == 1 and clk == 0:
128 self.handle_new_dac_bit()