2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
5 ## Copyright (C) 2013 Matt Ranostay <mranostay@gmail.com>
6 ## Copyright (C) 2014 alberink <alberink@stampfini.org>
8 ## This program is free software; you can redistribute it and/or modify
9 ## it under the terms of the GNU General Public License as published by
10 ## the Free Software Foundation; either version 2 of the License, or
11 ## (at your option) any later version.
13 ## This program is distributed in the hope that it will be useful,
14 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ## GNU General Public License for more details.
18 ## You should have received a copy of the GNU General Public License
19 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
22 import sigrokdecode as srd
24 NUM_OUTPUT_CHANNELS = 8
26 def logic_channels(num_channels):
28 for i in range(num_channels):
29 l.append(tuple(['p%d' % i, 'P-port input/output %d' % i]))
32 class Decoder(srd.Decoder):
36 longname = 'Texas Instruments TCA6408A'
37 desc = 'Texas Instruments TCA6408A 8-bit I²C I/O expander.'
41 tags = ['Embedded/industrial', 'IC']
43 ('register', 'Register type'),
44 ('value', 'Register value'),
45 ('warning', 'Warning'),
47 logic_output_channels = logic_channels(NUM_OUTPUT_CHANNELS)
49 ('regs', 'Registers', (0, 1)),
50 ('warnings', 'Warnings', (2,)),
60 self.logic_output_es = 0
64 self.out_ann = self.register(srd.OUTPUT_ANN)
65 self.out_logic = self.register(srd.OUTPUT_LOGIC)
68 self.put(self.ss, self.es, self.out_ann, data)
70 def put_logic_states(self):
71 if (self.es > self.logic_output_es):
72 data = bytes([self.logic_value])
73 self.put(self.logic_output_es, self.es, self.out_logic, [0, data])
74 self.logic_output_es = self.es
76 def handle_reg_0x00(self, b):
77 self.putx([1, ['State of inputs: %02X' % b]])
80 def handle_reg_0x01(self, b):
81 self.putx([1, ['Outputs set: %02X' % b]])
84 def handle_reg_0x02(self, b):
85 self.putx([1, ['Polarity inverted: %02X' % b]])
87 def handle_reg_0x03(self, b):
88 self.putx([1, ['Configuration: %02X' % b]])
90 def handle_write_reg(self, b):
92 self.putx([0, ['Input port', 'In', 'I']])
94 self.putx([0, ['Output port', 'Out', 'O']])
96 self.putx([0, ['Polarity inversion register', 'Pol', 'P']])
98 self.putx([0, ['Configuration register', 'Conf', 'C']])
100 def check_correct_chip(self, addr):
101 if addr not in (0x20, 0x21):
102 self.putx([2, ['Warning: I²C slave 0x%02X not a TCA6408A '
103 'compatible chip.' % addr]])
106 def decode(self, ss, es, data):
109 # Store the start/end samples of this I²C packet.
110 self.ss, self.es = ss, es
112 self.put_logic_states()
115 if self.state == 'IDLE':
116 # Wait for an I²C START condition.
119 self.state = 'GET SLAVE ADDR'
120 elif self.state == 'GET SLAVE ADDR':
122 self.state = 'GET REG ADDR'
123 elif self.state == 'GET REG ADDR':
124 # Wait for a data write (master selects the slave register).
125 if cmd in ('ADDRESS READ', 'ADDRESS WRITE'):
126 self.check_correct_chip(databyte)
127 if cmd != 'DATA WRITE':
130 self.handle_write_reg(self.reg)
131 self.state = 'WRITE IO REGS'
132 elif self.state == 'WRITE IO REGS':
133 # If we see a Repeated Start here, the master wants to read.
134 if cmd == 'START REPEAT':
135 self.state = 'READ IO REGS'
137 # Otherwise: Get data bytes until a STOP condition occurs.
138 if cmd == 'DATA WRITE':
139 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
144 elif self.state == 'READ IO REGS':
145 # Wait for an address read operation.
146 if cmd == 'ADDRESS READ':
147 self.state = 'READ IO REGS2'
150 elif self.state == 'READ IO REGS2':
151 if cmd == 'DATA READ':
152 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)