2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 import sigrokdecode as srd
28 [<cmd>, <data1>, <data2>]
31 - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
32 The data is _usually_ 8 bits (but can also be fewer or more bits).
33 Both data items are Python numbers (not strings), or None if the respective
34 probe was not supplied.
35 - 'BITS': <data1>/<data2> contain a list of bit values in this MISO/MOSI data
36 item, and for each of those also their respective start-/endsample numbers.
37 - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
38 Both data items are Python numbers (0/1), not strings.
43 ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88],
44 [1, 89, 90], [1, 91, 92], [1, 93, 94], [1, 95, 96]],
45 [[0, 80, 82], [1, 83, 84], [0, 85, 86], [1, 87, 88],
46 [1, 89, 90], [1, 91, 92], [0, 93, 94], [0, 95, 96]]]
53 # Key: (CPOL, CPHA). Value: SPI mode.
54 # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
55 # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
63 class Decoder(srd.Decoder):
67 longname = 'Serial Peripheral Interface'
68 desc = 'Full-duplex, synchronous, serial bus.'
73 {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
76 {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'},
77 {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'},
78 {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'},
81 {'id': 'cs_polarity', 'desc': 'CS# polarity', 'default': 'active-low',
82 'values': ('active-low', 'active-high')},
83 {'id': 'cpol', 'desc': 'Clock polarity', 'default': 0,
85 {'id': 'cpha', 'desc': 'Clock phase', 'default': 0,
87 {'id': 'bitorder', 'desc': 'Bit order',
88 'default': 'msb-first', 'values': ('msb-first', 'lsb-first')},
89 {'id': 'wordsize', 'desc': 'Word size', 'default': 8},
92 ('miso-data', 'MISO data'),
93 ('mosi-data', 'MOSI data'),
94 ('miso-bits', 'MISO bits'),
95 ('mosi-bits', 'MOSI bits'),
96 ('warnings', 'Human-readable warnings'),
99 ('miso-data', 'MISO data', (0,)),
100 ('miso-bits', 'MISO bits', (2,)),
101 ('mosi-data', 'MOSI data', (1,)),
102 ('mosi-bits', 'MOSI bits', (3,)),
103 ('other', 'Other', (4,)),
107 self.samplerate = None
110 self.misodata = self.mosidata = 0
113 self.startsample = -1
115 self.cs_was_deasserted = False
118 self.have_cs = self.have_miso = self.have_mosi = None
121 def metadata(self, key, value):
122 if key == srd.SRD_CONF_SAMPLERATE:
123 self.samplerate = value
126 self.out_python = self.register(srd.OUTPUT_PYTHON)
127 self.out_ann = self.register(srd.OUTPUT_ANN)
128 self.out_bitrate = self.register(srd.OUTPUT_META,
129 meta=(int, 'Bitrate', 'Bitrate during transfers'))
131 def putw(self, data):
132 self.put(self.startsample, self.samplenum, self.out_ann, data)
135 # Pass MISO and MOSI bits and then data to the next PD up the stack.
136 so = self.misodata if self.have_miso else None
137 si = self.mosidata if self.have_mosi else None
138 so_bits = self.misobits if self.have_miso else None
139 si_bits = self.mosibits if self.have_mosi else None
142 ss, es = self.misobits[-1][1], self.misobits[0][2]
144 ss, es = self.mosibits[-1][1], self.mosibits[0][2]
146 self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
147 self.put(ss, es, self.out_python, ['DATA', si, so])
151 for bit in self.misobits:
152 self.put(bit[1], bit[2], self.out_ann, [2, ['%d' % bit[0]]])
154 for bit in self.mosibits:
155 self.put(bit[1], bit[2], self.out_ann, [3, ['%d' % bit[0]]])
157 # Dataword annotations.
159 self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]])
161 self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]])
163 def reset_decoder_state(self):
164 self.misodata = 0 if self.have_miso else None
165 self.mosidata = 0 if self.have_mosi else None
166 self.misobits = [] if self.have_miso else None
167 self.mosibits = [] if self.have_mosi else None
170 def handle_bit(self, miso, mosi, clk, cs):
171 # If this is the first bit of a dataword, save its sample number.
172 if self.bitcount == 0:
173 self.startsample = self.samplenum
174 self.cs_was_deasserted = False
176 active_low = (self.options['cs_polarity'] == 'active-low')
177 deasserted = (cs == 1) if active_low else (cs == 0)
179 self.cs_was_deasserted = True
181 ws = self.options['wordsize']
183 # Receive MISO bit into our shift register.
185 if self.options['bitorder'] == 'msb-first':
186 self.misodata |= miso << (ws - 1 - self.bitcount)
188 self.misodata |= miso << self.bitcount
190 # Receive MOSI bit into our shift register.
192 if self.options['bitorder'] == 'msb-first':
193 self.mosidata |= mosi << (ws - 1 - self.bitcount)
195 self.mosidata |= mosi << self.bitcount
197 # Guesstimate the endsample for this bit (can be overridden below).
199 if self.bitcount > 0:
201 es += self.samplenum - self.misobits[0][1]
203 es += self.samplenum - self.mosibits[0][1]
206 self.misobits.insert(0, [miso, self.samplenum, es])
208 self.mosibits.insert(0, [mosi, self.samplenum, es])
210 if self.bitcount > 0 and self.have_miso:
211 self.misobits[1][2] = self.samplenum
212 if self.bitcount > 0 and self.have_mosi:
213 self.mosibits[1][2] = self.samplenum
217 # Continue to receive if not enough bits were received, yet.
218 if self.bitcount != ws:
224 elapsed = 1 / float(self.samplerate)
225 elapsed *= (self.samplenum - self.startsample + 1)
226 bitrate = int(1 / elapsed * self.options['wordsize'])
227 self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)
229 if self.have_cs and self.cs_was_deasserted:
230 self.putw([4, ['CS# was deasserted during this data word!']])
232 self.reset_decoder_state()
234 def find_clk_edge(self, miso, mosi, clk, cs):
235 if self.have_cs and self.oldcs != cs:
236 # Send all CS# pin value changes.
237 self.put(self.samplenum, self.samplenum, self.out_python,
238 ['CS-CHANGE', self.oldcs, cs])
240 # Reset decoder state when CS# changes (and the CS# pin is used).
241 self.reset_decoder_state()
243 # Ignore sample if the clock pin hasn't changed.
244 if clk == self.oldclk:
249 # Sample data on rising/falling clock edge (depends on mode).
250 mode = spi_mode[self.options['cpol'], self.options['cpha']]
251 if mode == 0 and clk == 0: # Sample on rising clock edge
253 elif mode == 1 and clk == 1: # Sample on falling clock edge
255 elif mode == 2 and clk == 1: # Sample on falling clock edge
257 elif mode == 3 and clk == 0: # Sample on rising clock edge
260 # Found the correct clock edge, now get the SPI bit(s).
261 self.handle_bit(miso, mosi, clk, cs)
263 def decode(self, ss, es, data):
264 if self.samplerate is None:
265 raise Exception("Cannot decode without samplerate.")
266 # Either MISO or MOSI can be omitted (but not both). CS# is optional.
267 for (self.samplenum, pins) in data:
269 # Ignore identical samples early on (for performance reasons).
270 if self.oldpins == pins:
272 self.oldpins, (clk, miso, mosi, cs) = pins, pins
273 self.have_miso = (miso in (0, 1))
274 self.have_mosi = (mosi in (0, 1))
275 self.have_cs = (cs in (0, 1))
277 # Either MISO or MOSI (but not both) can be omitted.
278 if not (self.have_miso or self.have_mosi):
279 raise Exception('Either MISO or MOSI (or both) pins required.')
282 if self.state == 'IDLE':
283 self.find_clk_edge(miso, mosi, clk, cs)
285 raise Exception('Invalid state: %s' % self.state)