2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 import sigrokdecode as srd
25 Protocol output format:
28 [<cmd>, <data1>, <data2>]
31 - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
32 The data is _usually_ 8 bits (but can also be fewer or more bits).
33 Both data items are Python numbers, not strings.
34 - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
35 Both data items are Python numbers (0/1), not strings.
44 # Key: (CPOL, CPHA). Value: SPI mode.
45 # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
46 # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
54 class Decoder(srd.Decoder):
58 longname = 'Serial Peripheral Interface'
59 desc = 'Full-duplex, synchronous, serial bus.'
64 {'id': 'miso', 'name': 'MISO',
65 'desc': 'SPI MISO line (Master in, slave out)'},
66 {'id': 'mosi', 'name': 'MOSI',
67 'desc': 'SPI MOSI line (Master out, slave in)'},
68 {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
71 {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'},
74 'cs_polarity': ['CS# polarity', 'active-low'],
75 'cpol': ['Clock polarity', 0],
76 'cpha': ['Clock phase', 0],
77 'bitorder': ['Bit order within the SPI data', 'msb-first'],
78 'wordsize': ['Word size of SPI data', 8], # 1-64?
79 'format': ['Data format', 'hex'],
82 ['miso-data', 'MISO SPI data'],
83 ['mosi-data', 'MOSI SPI data'],
84 ['warnings', 'Human-readable warnings'],
88 self.samplerate = None
95 self.cs_was_deasserted_during_data_word = 0
100 def metadata(self, key, value):
101 if key == srd.SRD_CONF_SAMPLERATE:
102 self.samplerate = value
105 self.out_proto = self.register(srd.OUTPUT_PYTHON)
106 self.out_ann = self.register(srd.OUTPUT_ANN)
107 self.out_bitrate = self.register(srd.OUTPUT_META,
108 meta=(int, 'Bitrate', 'Bitrate during transfers'))
110 def putpw(self, data):
111 self.put(self.startsample, self.samplenum, self.out_proto, data)
113 def putw(self, data):
114 self.put(self.startsample, self.samplenum, self.out_ann, data)
116 def handle_bit(self, miso, mosi, sck, cs):
117 # If this is the first bit, save its sample number.
118 if self.bitcount == 0:
119 self.startsample = self.samplenum
121 active_low = (self.options['cs_polarity'] == 'active-low')
122 deasserted = cs if active_low else not cs
124 self.cs_was_deasserted_during_data_word = 1
126 ws = self.options['wordsize']
128 # Receive MOSI bit into our shift register.
129 if self.options['bitorder'] == 'msb-first':
130 self.mosidata |= mosi << (ws - 1 - self.bitcount)
132 self.mosidata |= mosi << self.bitcount
134 # Receive MISO bit into our shift register.
135 if self.options['bitorder'] == 'msb-first':
136 self.misodata |= miso << (ws - 1 - self.bitcount)
138 self.misodata |= miso << self.bitcount
142 # Continue to receive if not enough bits were received, yet.
143 if self.bitcount != ws:
146 # Pass MOSI and MISO to the next PD up the stack
147 self.putpw(['DATA', self.mosidata, self.misodata])
150 self.putw([0, ['%02X' % self.misodata]])
151 self.putw([1, ['%02X' % self.mosidata]])
154 elapsed = 1 / float(self.samplerate) * (self.samplenum - self.startsample + 1)
155 bitrate = int(1 / elapsed * self.options['wordsize'])
156 self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)
158 if self.cs_was_deasserted_during_data_word:
159 self.putw([2, ['CS# was deasserted during this data word!']])
161 # Reset decoder state.
162 self.mosidata = self.misodata = self.bitcount = 0
164 def find_clk_edge(self, miso, mosi, sck, cs):
165 if self.have_cs and self.oldcs != cs:
166 # Send all CS# pin value changes.
167 self.put(self.samplenum, self.samplenum, self.out_proto,
168 ['CS-CHANGE', self.oldcs, cs])
170 # Reset decoder state when CS# changes (and the CS# pin is used).
171 self.mosidata = self.misodata = self.bitcount= 0
173 # Ignore sample if the clock pin hasn't changed.
174 if sck == self.oldsck:
179 # Sample data on rising/falling clock edge (depends on mode).
180 mode = spi_mode[self.options['cpol'], self.options['cpha']]
181 if mode == 0 and sck == 0: # Sample on rising clock edge
183 elif mode == 1 and sck == 1: # Sample on falling clock edge
185 elif mode == 2 and sck == 1: # Sample on falling clock edge
187 elif mode == 3 and sck == 0: # Sample on rising clock edge
190 # Found the correct clock edge, now get the SPI bit(s).
191 self.handle_bit(miso, mosi, sck, cs)
193 def decode(self, ss, es, data):
194 if self.samplerate is None:
195 raise Exception("Cannot decode without samplerate.")
196 # TODO: Either MISO or MOSI could be optional. CS# is optional.
197 for (self.samplenum, pins) in data:
199 # Ignore identical samples early on (for performance reasons).
200 if self.oldpins == pins:
202 self.oldpins, (miso, mosi, sck, cs) = pins, pins
203 self.have_cs = (cs in (0, 1))
206 if self.state == 'IDLE':
207 self.find_clk_edge(miso, mosi, sck, cs)
209 raise Exception('Invalid state: %s' % self.state)