2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2019 Shirow Miura <shirowmiura@gmail.com>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
41 START, STOP, CLOCK, DATA = range(4)
43 class Decoder(srd.Decoder):
47 longname = 'Signature analysis'
48 desc = 'Annotate signature of logic patterns.'
52 tags = ['Debug/trace', 'Util', 'Encoding']
54 {'id': 'start', 'name': 'START', 'desc': 'START channel'},
55 {'id': 'stop', 'name': 'STOP', 'desc': 'STOP channel'},
56 {'id': 'clk', 'name': 'CLOCK', 'desc': 'CLOCK channel'},
57 {'id': 'data', 'name': 'DATA', 'desc': 'DATA channel'},
60 {'id': 'start_edge', 'desc': 'START edge polarity',
61 'default': 'rising', 'values': ('rising', 'falling')},
62 {'id': 'stop_edge', 'desc': 'STOP edge polarity',
63 'default': 'rising', 'values': ('rising', 'falling')},
64 {'id': 'clk_edge', 'desc': 'CLOCK edge polarity',
65 'default': 'falling', 'values': ('rising', 'falling')},
66 {'id': 'annbits', 'desc': 'Enable bit level annotations',
67 'default': 'no', 'values': ('yes', 'no')},
77 ('bits', 'Bits', (0, 1, 2, 3)),
88 self.out_ann = self.register(srd.OUTPUT_ANN)
90 def putsig(self, ss, es, signature):
91 s = ''.join([symbol_map[(signature >> 0) & 0x0f],
92 symbol_map[(signature >> 4) & 0x0f],
93 symbol_map[(signature >> 8) & 0x0f],
94 symbol_map[(signature >> 12) & 0x0f]])
95 self.put(ss, es, self.out_ann, [4, [s]])
97 def putb(self, ss, ann):
98 self.put(ss, self.samplenum, self.out_ann, ann)
102 start_edge_mode_rising = opt['start_edge'] == 'rising'
103 stop_edge_mode_rising = opt['stop_edge'] == 'rising'
104 annbits = opt['annbits'] == 'yes'
109 prev_start = 0 if start_edge_mode_rising else 1
110 prev_stop = 0 if stop_edge_mode_rising else 1
114 start, stop, _, data = self.wait({CLOCK: opt['clk_edge']})
115 if start != prev_start and not gate_is_open:
116 gate_is_open = (start == 1) if start_edge_mode_rising else (start == 0)
119 sample_start = self.samplenum
121 elif stop != prev_stop and gate_is_open:
122 gate_is_open = not ((stop == 1) if stop_edge_mode_rising else (stop == 0))
126 self.putb(last_samplenum, [3, ['STOP', 'STP', 'P']])
127 self.putsig(sample_start, self.samplenum, shiftreg)
133 s = '<{}>'.format(data)
134 self.putb(last_samplenum, [2, ['START' + s, 'STR' + s, 'S' + s]])
137 self.putb(last_samplenum, [data, [str(data)]])
138 incoming = (bin(shiftreg & 0b0000_0010_1001_0001).count('1') + data) & 1
139 shiftreg = (incoming << 15) | (shiftreg >> 1)
142 last_samplenum = self.samplenum