2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # ST STM32 JTAG protocol decoder
23 import sigrokdecode as srd
25 # JTAG debug port data registers (in IR[3:0]) and their sizes (in bits)
26 # Note: The ARM DAP-DP is not IEEE 1149.1 (JTAG) compliant (as per ARM docs),
27 # as it does not implement the EXTEST, SAMPLE, and PRELOAD instructions.
28 # Instead, BYPASS is decoded for any of these instructions.
30 '1111': ['BYPASS', 1], # Bypass register
31 '1110': ['IDCODE', 32], # ID code register
32 '1010': ['DPACC', 35], # Debug port access register
33 '1011': ['APACC', 35], # Access port access register
34 '1000': ['ABORT', 35], # Abort register # TODO: 32 bits? Datasheet typo?
37 # ARM Cortex-M3 r1p1-01rel0 ID code
38 cm3_idcode = 0x3ba00477
40 # JTAG ID code in the STM32F10xxx BSC (boundary scan) TAP
42 0x06412041: 'Low-density device, rev. A',
43 0x06410041: 'Medium-density device, rev. A',
44 0x16410041: 'Medium-density device, rev. B/Z/Y',
45 0x06414041: 'High-density device, rev. A/Z/Y',
46 0x06430041: 'XL-density device, rev. A',
47 0x06418041: 'Connectivity-line device, rev. A/Z',
50 # ACK[2:0] in the DPACC/APACC registers (unlisted values are reserved)
56 # 32bit debug port registers (addressed via A[3:2])
58 '00': 'Reserved', # Must be kept at reset value
64 # APB-AP registers (each of them 32 bits wide)
66 0x00: ['CSW', 'Control/status word'],
67 0x04: ['TAR', 'Transfer address'],
69 0x0c: ['DRW', 'Data read/write'],
70 0x10: ['BD0', 'Banked data 0'],
71 0x14: ['BD1', 'Banked data 1'],
72 0x18: ['BD2', 'Banked data 2'],
73 0x1c: ['BD3', 'Banked data 3'],
74 # 0x20-0xf4: Reserved SBZ
75 0x800000000: ['ROM', 'Debug ROM address'],
76 0xfc: ['IDR', 'Identification register'],
79 # TODO: All start/end sample values in self.put() calls are bogus.
80 # TODO: Split off generic ARM/Cortex-M3 parts into another protocol decoder?
82 # Bits[31:28]: Version (here: 0x3)
83 # JTAG-DP: 0x3, SW-DP: 0x2
84 # Bits[27:12]: Part number (here: 0xba00)
85 # JTAG-DP: 0xba00, SW-DP: 0xba10
86 # Bits[11:1]: JEDEC (JEP-106) manufacturer ID (here: 0x23b)
87 # Bits[11:8]: Continuation code ('ARM Limited': 0x04)
88 # Bits[7:1]: Identity code ('ARM Limited': 0x3b)
89 # Bits[0:0]: Reserved (here: 0x1)
90 def decode_device_id_code(bits):
91 id_hex = '0x%x' % int('0b' + bits, 2)
92 ver = '0x%x' % int('0b' + bits[-32:-28], 2)
93 part = '0x%x' % int('0b' + bits[-28:-12], 2)
94 manuf = '0x%x' % int('0b' + bits[-12:-1], 2)
95 res = '0x%x' % int('0b' + bits[-1], 2)
96 return (id_hex, ver, part, manuf, res)
98 # DPACC is used to access debug port registers (CTRL/STAT, SELECT, RDBUFF).
99 # APACC is used to access all Access Port (AHB-AP) registers.
101 # APACC/DPACC, when transferring data IN:
102 # Bits[34:3] = DATA[31:0]: 32bit data to transfer (write request)
103 # Bits[2:1] = A[3:2]: 2-bit address (debug/access port register)
104 # Bits[0:0] = RnW: Read request (1) or write request (0)
105 def data_in(instruction, bits):
106 data, a, rnw = bits[:-3], bits[-3:-1], bits[-1]
107 data_hex = '0x%x' % int('0b' + data, 2)
108 r = 'Read request' if (rnw == '1') else 'Write request'
109 # reg = dp_reg[a] if (instruction == 'DPACC') else apb_ap_reg[a]
110 reg = dp_reg[a] if (instruction == 'DPACC') else a # TODO
111 return 'New transaction: DATA: %s, A: %s, RnW: %s' % (data_hex, reg, r)
113 # APACC/DPACC, when transferring data OUT:
114 # Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
115 # Bits[2:0] = ACK[2:0]: 3-bit acknowledge
117 data, ack = bits[:-3], bits[-3:]
118 data_hex = '0x%x' % int('0b' + data, 2)
119 ack_meaning = ack_val.get(ack, 'Reserved')
120 return 'Previous transaction result: DATA: %s, ACK: %s' \
121 % (data_hex, ack_meaning)
123 class Decoder(srd.Decoder):
126 name = 'JTAG / STM32'
127 longname = 'Joint Test Action Group / ST STM32'
128 desc = 'ST STM32-specific JTAG protocol.'
131 outputs = ['jtag_stm32']
136 ['Text', 'Human-readable text'],
139 def __init__(self, **kwargs):
141 # self.state = 'BYPASS'
143 def start(self, metadata):
144 # self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag_stm32')
145 self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag_stm32')
150 def handle_reg_bypass(self, cmd, bits):
152 self.put(self.ss, self.es, self.out_ann, [0, ['BYPASS: ' + bits]])
154 def handle_reg_idcode(self, cmd, bits):
156 # IDCODE is a read-only register which is always accessible.
157 # IR == IDCODE: The device ID code is shifted out via DR next.
158 self.put(self.ss, self.es, self.out_ann,
159 [0, ['IDCODE: %s (ver=%s, part=%s, manuf=%s, res=%s)' % \
160 decode_device_id_code(bits)]])
162 def handle_reg_dpacc(self, cmd, bits):
163 # self.put(self.ss, self.es, self.out_ann,
164 # [0, ['DPACC/%s: %s' % (cmd, bits)]])
165 s = data_in('DPACC', bits) if (cmd == 'DR TDI') else data_out(bits)
166 self.put(self.ss, self.es, self.out_ann, [0, [s]])
168 def handle_reg_apacc(self, cmd, bits):
169 # self.put(self.ss, self.es, self.out_ann,
170 # [0, ['APACC/%s: %s' % (cmd, bits)]])
171 s = data_in('APACC', bits) if (cmd == 'DR TDI') else data_out(bits)
172 self.put(self.ss, self.es, self.out_ann, [0, [s]])
174 def handle_reg_abort(self, cmd, bits):
175 # Bits[31:1]: reserved. Bit[0]: DAPABORT.
176 a = '' if (bits[0] == '1') else 'No '
177 s = 'DAPABORT = %s: %sDAP abort generated' % (bits[0], a)
178 self.put(self.ss, self.es, self.out_ann, [0, [s]])
180 # Warn if DAPABORT[31:1] contains non-zero bits.
181 if (bits[:-1] != ('0' * 31)):
182 self.put(self.ss, self.es, self.out_ann,
183 [0, ['WARNING: DAPABORT[31:1] reserved!']])
185 def handle_reg_unknown(self, cmd, bits):
186 self.put(self.ss, self.es, self.out_ann,
187 [0, ['Unknown instruction: ' % bits]]) # TODO
189 def decode(self, ss, es, data):
190 # Assumption: The right-most char in the 'val' bitstring is the LSB.
193 self.ss, self.es = ss, es
195 # self.put(self.ss, self.es, self.out_ann, [0, [cmd + ' / ' + val]])
198 if self.state == 'IDLE':
199 # Wait until a new instruction is shifted into the IR register.
202 # Switch to the state named after the instruction, or 'UNKNOWN'.
203 # Ignore bits other than IR[3:0]. While the IR register is only
204 # 4 bits in size, some programs (e.g. OpenOCD) might fill in a
205 # few more (dummy) bits. OpenOCD makes IR at least 8 bits long.
206 self.state = ir.get(val[-4:], ['UNKNOWN', 0])[0]
207 self.put(self.ss, self.es, self.out_ann, [0, ['IR: ' + self.state]])
208 elif self.state == 'BYPASS':
209 # Here we're interested in incoming bits (TDI).
212 handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
215 elif self.state in ('IDCODE', 'ABORT', 'UNKNOWN'):
216 # Here we're interested in outgoing bits (TDO).
219 handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
222 elif self.state in ('DPACC', 'APACC'):
223 # Here we're interested in incoming and outgoing bits (TDI/TDO).
224 if cmd not in ('DR TDI', 'DR TDO'):
226 handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
228 if cmd == 'DR TDO': # TODO: Assumes 'DR TDI' comes before 'DR TDO'
231 raise Exception('Invalid state: %s' % self.state)