2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # JTAG protocol decoder
23 import sigrokdecode as srd
27 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE',
29 'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR',
30 'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR',
32 'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR',
33 'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR',
36 def get_annotation_classes():
39 l.append([s.lower(), s])
42 class Decoder(srd.Decoder):
46 longname = 'Joint Test Action Group (IEEE 1149.1)'
47 desc = 'Protocol for testing, debugging, and flashing ICs.'
52 {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'},
53 {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'},
54 {'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
55 {'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
58 {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
59 {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
60 {'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'},
63 annotations = get_annotation_classes()
65 def __init__(self, **kwargs):
66 # self.state = 'TEST-LOGIC-RESET'
67 self.state = 'RUN-TEST/IDLE'
69 self.oldpins = (-1, -1, -1, -1)
74 self.ss_item = self.es_item = None
75 self.saved_item = None
79 self.out_proto = self.register(srd.OUTPUT_PYTHON)
80 self.out_ann = self.register(srd.OUTPUT_ANN)
83 self.put(self.ss_item, self.es_item, self.out_ann, data)
86 self.put(self.ss_item, self.es_item, self.out_proto, data)
88 def advance_state_machine(self, tms):
89 self.oldstate = self.state
92 if self.state == 'TEST-LOGIC-RESET':
93 self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
94 elif self.state == 'RUN-TEST/IDLE':
95 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
98 elif self.state == 'SELECT-DR-SCAN':
99 self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
100 elif self.state == 'CAPTURE-DR':
101 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
102 elif self.state == 'SHIFT-DR':
103 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
104 elif self.state == 'EXIT1-DR':
105 self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
106 elif self.state == 'PAUSE-DR':
107 self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
108 elif self.state == 'EXIT2-DR':
109 self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
110 elif self.state == 'UPDATE-DR':
111 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
114 elif self.state == 'SELECT-IR-SCAN':
115 self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
116 elif self.state == 'CAPTURE-IR':
117 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
118 elif self.state == 'SHIFT-IR':
119 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
120 elif self.state == 'EXIT1-IR':
121 self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
122 elif self.state == 'PAUSE-IR':
123 self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
124 elif self.state == 'EXIT2-IR':
125 self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
126 elif self.state == 'UPDATE-IR':
127 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
130 raise Exception('Invalid state: %s' % self.state)
132 def handle_rising_tck_edge(self, tdi, tdo, tck, tms):
133 # Rising TCK edges always advance the state machine.
134 self.advance_state_machine(tms)
136 if self.first == True:
137 # Save the start sample and item for later (no output yet).
138 self.ss_item = self.samplenum
140 self.saved_item = self.state
142 # Output the saved item (from the last CLK edge to the current).
143 self.es_item = self.samplenum
144 # Output the state we just switched to.
145 self.putx([jtag_states.index(self.state), [self.state]])
146 self.putp(['NEW STATE', self.state])
147 self.ss_item = self.samplenum
148 self.saved_item = self.state
150 # If we went from SHIFT-IR to SHIFT-IR, or SHIFT-DR to SHIFT-DR,
151 # collect the current TDI/TDO values (upon rising TCK edge).
152 if self.state.startswith('SHIFT-') and self.oldstate == self.state:
153 self.bits_tdi.insert(0, tdi)
154 self.bits_tdo.insert(0, tdo)
155 # TODO: ANN/PROTO output.
156 # self.putx([0, ['TDI add: ' + str(tdi)]])
157 # self.putp([0, ['TDO add: ' + str(tdo)]])
159 # Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*.
160 if self.oldstate.startswith('SHIFT-') and \
161 self.state.startswith('EXIT1-'):
163 t = self.state[-2:] + ' TDI'
164 b = ''.join(map(str, self.bits_tdi))
165 h = ' (0x%x' % int('0b' + b, 2) + ')'
166 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi)) + ' bits'
167 # self.putx([0, [s]])
171 t = self.state[-2:] + ' TDO'
172 b = ''.join(map(str, self.bits_tdo))
173 h = ' (0x%x' % int('0b' + b, 2) + ')'
174 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo)) + ' bits'
175 # self.putx([0, [s]])
179 def decode(self, ss, es, data):
180 for (self.samplenum, pins) in data:
182 # If none of the pins changed, there's nothing to do.
183 if self.oldpins == pins:
186 # Store current pin values for the next round.
189 # Get individual pin values into local variables.
190 # Unused probes will have a value of > 1.
191 (tdi, tdo, tck, tms, trst, srst, rtck) = pins
193 # We only care about TCK edges (either rising or falling).
194 if (self.oldtck == tck):
197 # Store start/end sample for later usage.
198 self.ss, self.es = ss, es
200 # self.putx([0, ['tdi:%s, tdo:%s, tck:%s, tms:%s' \
201 # % (tdi, tdo, tck, tms)]])
203 if (self.oldtck == 0 and tck == 1):
204 self.handle_rising_tck_edge(tdi, tdo, tck, tms)