2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # I2C protocol decoder
23 # TODO: Look into arbitration, collision detection, clock synchronisation, etc.
24 # TODO: Handle clock stretching.
25 # TODO: Handle combined messages / repeated START.
26 # TODO: Implement support for 7bit and 10bit slave addresses.
27 # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
28 # TODO: Implement support for detecting various bus errors.
29 # TODO: I2C address of slaves.
30 # TODO: Handle multiple different I2C devices on same bus
31 # -> we need to decode multiple protocols at the same time.
33 import sigrokdecode as srd
35 # Annotation feed formats
40 # Values are verbose and short annotation, respectively.
42 'START': ['START', 'S'],
43 'START REPEAT': ['START REPEAT', 'Sr'],
44 'STOP': ['STOP', 'P'],
46 'NACK': ['NACK', 'N'],
47 'ADDRESS READ': ['ADDRESS READ', 'AR'],
48 'ADDRESS WRITE': ['ADDRESS WRITE', 'AW'],
49 'DATA READ': ['DATA READ', 'DR'],
50 'DATA WRITE': ['DATA WRITE', 'DW'],
53 class Decoder(srd.Decoder):
57 longname = 'Inter-Integrated Circuit'
58 desc = 'Two-wire, multi-master, serial bus.'
63 {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
64 {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
68 'addressing': ['Slave addressing (in bits)', 7], # 7 or 10
73 'Read/write bit shifted out from the 8-bit I2C slave address'],
75 ['7-bit shifted hex (short)',
76 'Read/write bit shifted out from the 8-bit I2C slave address'],
78 ['Raw hex', 'Unaltered raw data'],
81 def __init__(self, **kwargs):
87 self.is_repeat_start = 0
88 self.state = 'FIND START'
92 def start(self, metadata):
93 self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
94 self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c')
99 def is_start_condition(self, scl, sda):
100 # START condition (S): SDA = falling, SCL = high
101 if (self.oldsda == 1 and sda == 0) and scl == 1:
105 def is_data_bit(self, scl, sda):
106 # Data sampling of receiver: SCL = rising
107 if self.oldscl == 0 and scl == 1:
111 def is_stop_condition(self, scl, sda):
112 # STOP condition (P): SDA = rising, SCL = high
113 if (self.oldsda == 0 and sda == 1) and scl == 1:
117 def found_start(self, scl, sda):
118 self.startsample = self.samplenum
120 cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START'
121 self.put(self.out_proto, [cmd, None])
122 self.put(self.out_ann, [ANN_SHIFTED, [proto[cmd][0]]])
123 self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto[cmd][1]]])
125 self.state = 'FIND ADDRESS'
126 self.bitcount = self.databyte = 0
127 self.is_repeat_start = 1
130 # Gather 8 bits of data plus the ACK/NACK bit.
131 def found_address_or_data(self, scl, sda):
132 # Address and data are transmitted MSB-first.
136 if self.bitcount == 0:
137 self.startsample = self.samplenum
139 # Return if we haven't collected all 8 + 1 bits, yet.
141 if self.bitcount != 8:
144 # We triggered on the ACK/NACK bit, but won't report that until later.
145 self.startsample -= 1
147 # Send raw output annotation before we start shifting out
148 # read/write and ACK/NACK bits.
149 self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]])
151 if self.state == 'FIND ADDRESS':
152 # The READ/WRITE bit is only in address bytes, not data bytes.
153 self.wr = 0 if (self.databyte & 1) else 1
154 d = self.databyte >> 1
155 elif self.state == 'FIND DATA':
158 if self.state == 'FIND ADDRESS' and self.wr == 1:
159 cmd = 'ADDRESS WRITE'
160 elif self.state == 'FIND ADDRESS' and self.wr == 0:
162 elif self.state == 'FIND DATA' and self.wr == 1:
164 elif self.state == 'FIND DATA' and self.wr == 0:
167 self.put(self.out_proto, [cmd, d])
168 self.put(self.out_ann, [ANN_SHIFTED, [proto[cmd][0], '0x%02x' % d]])
169 self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto[cmd][1], '0x%02x' % d]])
171 # Done with this packet.
172 self.startsample = -1
173 self.bitcount = self.databyte = 0
174 self.state = 'FIND ACK'
176 def get_ack(self, scl, sda):
177 self.startsample = self.samplenum
178 ack_bit = 'NACK' if (sda == 1) else 'ACK'
179 self.put(self.out_proto, [ack_bit, None])
180 self.put(self.out_ann, [ANN_SHIFTED, [proto[ack_bit][0]]])
181 self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto[ack_bit][1]]])
182 # There could be multiple data bytes in a row, so either find
183 # another data byte or a STOP condition next.
184 self.state = 'FIND DATA'
186 def found_stop(self, scl, sda):
187 self.startsample = self.samplenum
188 self.put(self.out_proto, ['STOP', None])
189 self.put(self.out_ann, [ANN_SHIFTED, [proto['STOP'][0]]])
190 self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto['STOP'][1]]])
192 self.state = 'FIND START'
193 self.is_repeat_start = 0
196 def put(self, output_id, data):
197 # Inject sample range into the call up to sigrok.
198 super(Decoder, self).put(self.startsample, self.samplenum, output_id, data)
200 def decode(self, ss, es, data):
201 for (self.samplenum, (scl, sda)) in data:
203 # First sample: Save SCL/SDA value.
204 if self.oldscl == None:
209 # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
212 if self.state == 'FIND START':
213 if self.is_start_condition(scl, sda):
214 self.found_start(scl, sda)
215 elif self.state == 'FIND ADDRESS':
216 if self.is_data_bit(scl, sda):
217 self.found_address_or_data(scl, sda)
218 elif self.state == 'FIND DATA':
219 if self.is_data_bit(scl, sda):
220 self.found_address_or_data(scl, sda)
221 elif self.is_start_condition(scl, sda):
222 self.found_start(scl, sda)
223 elif self.is_stop_condition(scl, sda):
224 self.found_stop(scl, sda)
225 elif self.state == 'FIND ACK':
226 if self.is_data_bit(scl, sda):
227 self.get_ack(scl, sda)
229 raise Exception('Invalid state %d' % self.STATE)
231 # Save current SDA/SCL values for the next round.