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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | ## | |
19 | ||
20 | import sigrokdecode as srd | |
21 | ||
22 | dacs = { | |
23 | 0: 'DACA', | |
24 | 1: 'DACB', | |
25 | 2: 'DACC', | |
26 | 3: 'DACD', | |
27 | } | |
28 | ||
29 | class Decoder(srd.Decoder): | |
30 | api_version = 3 | |
31 | id = 'tlc5620' | |
32 | name = 'TI TLC5620' | |
33 | longname = 'Texas Instruments TLC5620' | |
34 | desc = 'Texas Instruments TLC5620 8-bit quad DAC.' | |
35 | license = 'gplv2+' | |
36 | inputs = ['logic'] | |
37 | outputs = [] | |
38 | tags = ['IC', 'Analog/digital'] | |
39 | channels = ( | |
40 | {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'}, | |
41 | {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'}, | |
42 | ) | |
43 | optional_channels = ( | |
44 | {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'}, | |
45 | {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'}, | |
46 | ) | |
47 | options = ( | |
48 | {'id': 'vref_a', 'desc': 'Reference voltage DACA (V)', 'default': 3.3}, | |
49 | {'id': 'vref_b', 'desc': 'Reference voltage DACB (V)', 'default': 3.3}, | |
50 | {'id': 'vref_c', 'desc': 'Reference voltage DACC (V)', 'default': 3.3}, | |
51 | {'id': 'vref_d', 'desc': 'Reference voltage DACD (V)', 'default': 3.3}, | |
52 | ) | |
53 | annotations = ( | |
54 | ('dac-select', 'DAC select'), | |
55 | ('gain', 'Gain'), | |
56 | ('value', 'DAC value'), | |
57 | ('data-latch', 'Data latch point'), | |
58 | ('ldac-fall', 'LDAC falling edge'), | |
59 | ('bit', 'Bit'), | |
60 | ('reg-write', 'Register write'), | |
61 | ('voltage-update', 'Voltage update'), | |
62 | ('voltage-update-all', 'Voltage update (all DACs)'), | |
63 | ('invalid-cmd', 'Invalid command'), | |
64 | ) | |
65 | annotation_rows = ( | |
66 | ('bits', 'Bits', (5,)), | |
67 | ('fields', 'Fields', (0, 1, 2)), | |
68 | ('registers', 'Registers', (6, 7)), | |
69 | ('voltage-updates', 'Voltage updates', (8,)), | |
70 | ('events', 'Events', (3, 4)), | |
71 | ('errors', 'Errors', (9,)), | |
72 | ) | |
73 | ||
74 | def __init__(self): | |
75 | self.reset() | |
76 | ||
77 | def reset(self): | |
78 | self.bits = [] | |
79 | self.ss_dac_first = None | |
80 | self.ss_dac = self.es_dac = 0 | |
81 | self.ss_gain = self.es_gain = 0 | |
82 | self.ss_value = self.es_value = 0 | |
83 | self.dac_select = self.gain = self.dac_value = None | |
84 | self.dacval = {'A': '?', 'B': '?', 'C': '?', 'D': '?'} | |
85 | self.gains = {'A': '?', 'B': '?', 'C': '?', 'D': '?'} | |
86 | ||
87 | def start(self): | |
88 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
89 | ||
90 | def handle_11bits(self): | |
91 | # Only look at the last 11 bits, the rest is ignored by the TLC5620. | |
92 | if len(self.bits) > 11: | |
93 | self.bits = self.bits[-11:] | |
94 | ||
95 | # If there are less than 11 bits, something is probably wrong. | |
96 | if len(self.bits) < 11: | |
97 | ss, es = self.samplenum, self.samplenum | |
98 | if len(self.bits) >= 2: | |
99 | ss = self.bits[0][1] | |
100 | es = self.bits[-1][1] + (self.bits[1][1] - self.bits[0][1]) | |
101 | self.put(ss, es, self.out_ann, [9, ['Command too short']]) | |
102 | self.bits = [] | |
103 | return False | |
104 | ||
105 | self.ss_dac = self.bits[0][1] | |
106 | self.es_dac = self.ss_gain = self.bits[2][1] | |
107 | self.es_gain = self.ss_value = self.bits[3][1] | |
108 | self.clock_width = self.es_gain - self.ss_gain | |
109 | self.es_value = self.bits[10][1] + self.clock_width # Guessed. | |
110 | ||
111 | if self.ss_dac_first is None: | |
112 | self.ss_dac_first = self.ss_dac | |
113 | ||
114 | s = ''.join(str(i[0]) for i in self.bits[:2]) | |
115 | self.dac_select = s = dacs[int(s, 2)] | |
116 | self.put(self.ss_dac, self.es_dac, self.out_ann, | |
117 | [0, ['DAC select: %s' % s, 'DAC sel: %s' % s, | |
118 | 'DAC: %s' % s, 'D: %s' % s, s, s[3]]]) | |
119 | ||
120 | self.gain = g = 1 + self.bits[2][0] | |
121 | self.put(self.ss_gain, self.es_gain, self.out_ann, | |
122 | [1, ['Gain: x%d' % g, 'G: x%d' % g, 'x%d' % g]]) | |
123 | ||
124 | s = ''.join(str(i[0]) for i in self.bits[3:]) | |
125 | self.dac_value = v = int(s, 2) | |
126 | self.put(self.ss_value, self.es_value, self.out_ann, | |
127 | [2, ['DAC value: %d' % v, 'Value: %d' % v, 'Val: %d' % v, | |
128 | 'V: %d' % v, '%d' % v]]) | |
129 | ||
130 | # Emit an annotation for each bit. | |
131 | for i in range(1, 11): | |
132 | self.put(self.bits[i - 1][1], self.bits[i][1], self.out_ann, | |
133 | [5, [str(self.bits[i - 1][0])]]) | |
134 | self.put(self.bits[10][1], self.bits[10][1] + self.clock_width, | |
135 | self.out_ann, [5, [str(self.bits[10][0])]]) | |
136 | ||
137 | self.bits = [] | |
138 | ||
139 | return True | |
140 | ||
141 | def handle_falling_edge_load(self): | |
142 | if not self.handle_11bits(): | |
143 | return | |
144 | s, v, g = self.dac_select, self.dac_value, self.gain | |
145 | self.put(self.samplenum, self.samplenum, self.out_ann, | |
146 | [3, ['Falling edge on LOAD', 'LOAD fall', 'F']]) | |
147 | vref = self.options['vref_%s' % self.dac_select[3].lower()] | |
148 | v = '%.2fV' % (vref * (v / 256) * self.gain) | |
149 | if self.ldac == 0: | |
150 | # If LDAC is low, the voltage is set immediately. | |
151 | self.put(self.ss_dac, self.es_value, self.out_ann, | |
152 | [7, ['Setting %s voltage to %s' % (s, v), | |
153 | '%s=%s' % (s, v)]]) | |
154 | else: | |
155 | # If LDAC is high, the voltage is not set immediately, but rather | |
156 | # stored in a register. When LDAC goes low all four DAC voltages | |
157 | # (DAC A/B/C/D) will be set at the same time. | |
158 | self.put(self.ss_dac, self.es_value, self.out_ann, | |
159 | [6, ['Setting %s register value to %s' % \ | |
160 | (s, v), '%s=%s' % (s, v)]]) | |
161 | # Save the last value the respective DAC was set to. | |
162 | self.dacval[self.dac_select[-1]] = str(self.dac_value) | |
163 | self.gains[self.dac_select[-1]] = self.gain | |
164 | ||
165 | def handle_falling_edge_ldac(self): | |
166 | self.put(self.samplenum, self.samplenum, self.out_ann, | |
167 | [4, ['Falling edge on LDAC', 'LDAC fall', 'LDAC', 'L']]) | |
168 | ||
169 | # Don't emit any annotations if we didn't see any register writes. | |
170 | if self.ss_dac_first is None: | |
171 | return | |
172 | ||
173 | # Calculate voltages based on Vref and the per-DAC gain. | |
174 | dacval = {} | |
175 | for key, val in self.dacval.items(): | |
176 | if val == '?': | |
177 | dacval[key] = '?' | |
178 | else: | |
179 | vref = self.options['vref_%s' % key.lower()] | |
180 | v = vref * (int(val) / 256) * self.gains[key] | |
181 | dacval[key] = '%.2fV' % v | |
182 | ||
183 | s = ''.join(['DAC%s=%s ' % (d, dacval[d]) for d in 'ABCD']).strip() | |
184 | self.put(self.ss_dac_first, self.samplenum, self.out_ann, | |
185 | [8, ['Updating voltages: %s' % s, s, s.replace('DAC', '')]]) | |
186 | self.ss_dac_first = None | |
187 | ||
188 | def handle_new_dac_bit(self, datapin): | |
189 | self.bits.append([datapin, self.samplenum]) | |
190 | ||
191 | def decode(self): | |
192 | while True: | |
193 | # DATA is shifted in the DAC on the falling CLK edge (MSB-first). | |
194 | # A falling edge of LOAD will latch the data. | |
195 | ||
196 | # Wait for one (or multiple) of the following conditions: | |
197 | # a) Falling edge on CLK, and/or | |
198 | # b) Falling edge on LOAD, and/or | |
199 | # b) Falling edge on LDAC | |
200 | pins = self.wait([{0: 'f'}, {2: 'f'}, {3: 'f'}]) | |
201 | self.ldac = pins[3] | |
202 | ||
203 | # Handle those conditions (one or more) that matched this time. | |
204 | if self.matched[0]: | |
205 | self.handle_new_dac_bit(pins[1]) | |
206 | if self.matched[1]: | |
207 | self.handle_falling_edge_load() | |
208 | if self.matched[2]: | |
209 | self.handle_falling_edge_ldac() |