]>
Commit | Line | Data |
---|---|---|
1 | ## | |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
5 | ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de> | |
6 | ## | |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
18 | ## along with this program; if not, write to the Free Software | |
19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | ## | |
21 | ||
22 | # SPI protocol decoder | |
23 | ||
24 | import sigrokdecode as srd | |
25 | ||
26 | # Key: (CPOL, CPHA). Value: SPI mode. | |
27 | # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive. | |
28 | # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge. | |
29 | spi_mode = { | |
30 | (0, 0): 0, # Mode 0 | |
31 | (0, 1): 1, # Mode 1 | |
32 | (1, 0): 2, # Mode 2 | |
33 | (1, 1): 3, # Mode 3 | |
34 | } | |
35 | ||
36 | # Annotation formats | |
37 | ANN_HEX = 0 | |
38 | ||
39 | class Decoder(srd.Decoder): | |
40 | api_version = 1 | |
41 | id = 'spi' | |
42 | name = 'SPI' | |
43 | longname = 'Serial Peripheral Interface' | |
44 | desc = 'Full-duplex, synchronous, serial bus.' | |
45 | license = 'gplv2+' | |
46 | inputs = ['logic'] | |
47 | outputs = ['spi'] | |
48 | probes = [ | |
49 | {'id': 'miso', 'name': 'MISO', | |
50 | 'desc': 'SPI MISO line (Master in, slave out)'}, | |
51 | {'id': 'mosi', 'name': 'MOSI', | |
52 | 'desc': 'SPI MOSI line (Master out, slave in)'}, | |
53 | {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, | |
54 | {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'}, | |
55 | ] | |
56 | optional_probes = [] # TODO | |
57 | options = { | |
58 | 'cs_polarity': ['CS# polarity', 'active-low'], | |
59 | 'cpol': ['Clock polarity', 0], | |
60 | 'cpha': ['Clock phase', 0], | |
61 | 'bitorder': ['Bit order within the SPI data', 'msb-first'], | |
62 | 'wordsize': ['Word size of SPI data', 8], # 1-64? | |
63 | } | |
64 | annotations = [ | |
65 | ['Hex', 'SPI data bytes in hex format'], | |
66 | ] | |
67 | ||
68 | def __init__(self): | |
69 | self.oldsck = 1 | |
70 | self.bitcount = 0 | |
71 | self.mosidata = 0 | |
72 | self.misodata = 0 | |
73 | self.bytesreceived = 0 | |
74 | self.samplenum = -1 | |
75 | self.cs_was_deasserted_during_data_word = 0 | |
76 | self.oldcs = -1 | |
77 | ||
78 | def start(self, metadata): | |
79 | self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') | |
80 | self.out_ann = self.add(srd.OUTPUT_ANN, 'spi') | |
81 | ||
82 | def report(self): | |
83 | return 'SPI: %d bytes received' % self.bytesreceived | |
84 | ||
85 | def decode(self, ss, es, data): | |
86 | # TODO: Either MISO or MOSI could be optional. CS# is optional. | |
87 | for (self.samplenum, (miso, mosi, sck, cs)) in data: | |
88 | ||
89 | if self.oldcs != cs: | |
90 | # Send all CS# pin value changes. | |
91 | self.put(self.samplenum, self.samplenum, self.out_proto, | |
92 | ['CS-CHANGE', self.oldcs, cs]) | |
93 | self.put(self.samplenum, self.samplenum, self.out_ann, | |
94 | [0, ['CS-CHANGE: %d->%d' % (self.oldcs, cs)]]) | |
95 | self.oldcs = cs | |
96 | ||
97 | # Ignore sample if the clock pin hasn't changed. | |
98 | if sck == self.oldsck: | |
99 | continue | |
100 | ||
101 | self.oldsck = sck | |
102 | ||
103 | # Sample data on rising/falling clock edge (depends on mode). | |
104 | mode = spi_mode[self.options['cpol'], self.options['cpha']] | |
105 | if mode == 0 and sck == 0: # Sample on rising clock edge | |
106 | continue | |
107 | elif mode == 1 and sck == 1: # Sample on falling clock edge | |
108 | continue | |
109 | elif mode == 2 and sck == 1: # Sample on falling clock edge | |
110 | continue | |
111 | elif mode == 3 and sck == 0: # Sample on rising clock edge | |
112 | continue | |
113 | ||
114 | # If this is the first bit, save its sample number. | |
115 | if self.bitcount == 0: | |
116 | self.start_sample = self.samplenum | |
117 | active_low = (self.options['cs_polarity'] == 'active-low') | |
118 | deasserted = cs if active_low else not cs | |
119 | if deasserted: | |
120 | self.cs_was_deasserted_during_data_word = 1 | |
121 | ||
122 | ws = self.options['wordsize'] | |
123 | ||
124 | # Receive MOSI bit into our shift register. | |
125 | if self.options['bitorder'] == 'msb-first': | |
126 | self.mosidata |= mosi << (ws - 1 - self.bitcount) | |
127 | else: | |
128 | self.mosidata |= mosi << self.bitcount | |
129 | ||
130 | # Receive MISO bit into our shift register. | |
131 | if self.options['bitorder'] == 'msb-first': | |
132 | self.misodata |= miso << (ws - 1 - self.bitcount) | |
133 | else: | |
134 | self.misodata |= miso << self.bitcount | |
135 | ||
136 | self.bitcount += 1 | |
137 | ||
138 | # Continue to receive if not enough bits were received, yet. | |
139 | if self.bitcount != ws: | |
140 | continue | |
141 | ||
142 | self.put(self.start_sample, self.samplenum, self.out_proto, | |
143 | ['DATA', self.mosidata, self.misodata]) | |
144 | self.put(self.start_sample, self.samplenum, self.out_ann, | |
145 | [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata, | |
146 | self.misodata)]]) | |
147 | ||
148 | if self.cs_was_deasserted_during_data_word: | |
149 | self.put(self.start_sample, self.samplenum, self.out_ann, | |
150 | [ANN_HEX, ['WARNING: CS# was deasserted during this ' | |
151 | 'SPI data byte!']]) | |
152 | ||
153 | # Reset decoder state. | |
154 | self.mosidata = 0 | |
155 | self.misodata = 0 | |
156 | self.bitcount = 0 | |
157 | ||
158 | # Keep stats for summary. | |
159 | self.bytesreceived += 1 | |
160 |