[libsigrokdecode.git] / decoders / spi / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# SPI protocol decoder

import sigrokdecode as srd

# Key: (CPOL, CPHA). Value: SPI mode.
# Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
# Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
spi_mode = {
    (0, 0): 0, # Mode 0
    (0, 1): 1, # Mode 1
    (1, 0): 2, # Mode 2
    (1, 1): 3, # Mode 3
}

class Decoder(srd.Decoder):
    api_version = 1
    id = 'spi'
    name = 'SPI'
    longname = 'Serial Peripheral Interface'
    desc = 'Full-duplex, synchronous, serial bus.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['spi']
    probes = [
        {'id': 'miso', 'name': 'MISO',
         'desc': 'SPI MISO line (Master in, slave out)'},
        {'id': 'mosi', 'name': 'MOSI',
         'desc': 'SPI MOSI line (Master out, slave in)'},
        {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
    ]
    optional_probes = [
        {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'},
    ]
    options = {
        'cs_polarity': ['CS# polarity', 'active-low'],
        'cpol': ['Clock polarity', 0],
        'cpha': ['Clock phase', 0],
        'bitorder': ['Bit order within the SPI data', 'msb-first'],
        'wordsize': ['Word size of SPI data', 8], # 1-64?
        'format': ['Data format', 'hex'],
    }
    annotations = [
        ['MISO/MOSI data', 'MISO/MOSI SPI data'],
        ['MISO data', 'MISO SPI data'],
        ['MOSI data', 'MOSI SPI data'],
        ['Warnings', 'Human-readable warnings'],
    ]

    def __init__(self):
        self.oldsck = 1
        self.bitcount = 0
        self.mosidata = 0
        self.misodata = 0
        self.bytesreceived = 0
        self.startsample = -1
        self.samplenum = -1
        self.cs_was_deasserted_during_data_word = 0
        self.oldcs = -1
        self.oldpins = None
        self.state = 'IDLE'

    def start(self, metadata):
        self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
        self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')

    def report(self):
        return 'SPI: %d bytes received' % self.bytesreceived

    def putpw(self, data):
        self.put(self.startsample, self.samplenum, self.out_proto, data)

    def putw(self, data):
        self.put(self.startsample, self.samplenum, self.out_ann, data)

    def handle_bit(self, miso, mosi, sck, cs):
        # If this is the first bit, save its sample number.
        if self.bitcount == 0:
            self.startsample = self.samplenum
            if self.have_cs:
                active_low = (self.options['cs_polarity'] == 'active-low')
                deasserted = cs if active_low else not cs
                if deasserted:
                    self.cs_was_deasserted_during_data_word = 1

        ws = self.options['wordsize']

        # Receive MOSI bit into our shift register.
        if self.options['bitorder'] == 'msb-first':
            self.mosidata |= mosi << (ws - 1 - self.bitcount)
        else:
            self.mosidata |= mosi << self.bitcount

        # Receive MISO bit into our shift register.
        if self.options['bitorder'] == 'msb-first':
            self.misodata |= miso << (ws - 1 - self.bitcount)
        else:
            self.misodata |= miso << self.bitcount

        self.bitcount += 1

        # Continue to receive if not enough bits were received, yet.
        if self.bitcount != ws:
            return

        self.putpw(['DATA', self.mosidata, self.misodata])
        self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]])
        self.putw([1, ['%02X' % self.misodata]])
        self.putw([2, ['%02X' % self.mosidata]])

        if self.cs_was_deasserted_during_data_word:
            self.putw([3, ['CS# was deasserted during this data word!']])

        # Reset decoder state.
        self.mosidata = self.misodata = self.bitcount = 0

        # Keep stats for summary.
        self.bytesreceived += 1

    def find_clk_edge(self, miso, mosi, sck, cs):
        if self.have_cs and self.oldcs != cs:
            # Send all CS# pin value changes.
            self.put(self.samplenum, self.samplenum, self.out_proto,
                     ['CS-CHANGE', self.oldcs, cs])
            self.oldcs = cs
            # Reset decoder state when CS# changes (and the CS# pin is used).
            self.mosidata = self.misodata = self.bitcount= 0

        # Ignore sample if the clock pin hasn't changed.
        if sck == self.oldsck:
            return

        self.oldsck = sck

        # Sample data on rising/falling clock edge (depends on mode).
        mode = spi_mode[self.options['cpol'], self.options['cpha']]
        if mode == 0 and sck == 0:   # Sample on rising clock edge
            return
        elif mode == 1 and sck == 1: # Sample on falling clock edge
            return
        elif mode == 2 and sck == 1: # Sample on falling clock edge
            return
        elif mode == 3 and sck == 0: # Sample on rising clock edge
            return

        # Found the correct clock edge, now get the SPI bit(s).
        self.handle_bit(miso, mosi, sck, cs)

    def decode(self, ss, es, data):
        # TODO: Either MISO or MOSI could be optional. CS# is optional.
        for (self.samplenum, pins) in data:

            # Ignore identical samples early on (for performance reasons).
            if self.oldpins == pins:
                continue
            self.oldpins, (miso, mosi, sck, cs) = pins, pins
            self.have_cs = (cs in (0, 1))

            # State machine.
            if self.state == 'IDLE':
                self.find_clk_edge(miso, mosi, sck, cs)
            else:
                raise Exception('Invalid state: %s' % self.state)
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
	5	## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
	6	##
	7	## This program is free software; you can redistribute it and/or modify
	8	## it under the terms of the GNU General Public License as published by
	9	## the Free Software Foundation; either version 2 of the License, or
	10	## (at your option) any later version.
	11	##
	12	## This program is distributed in the hope that it will be useful,
	13	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	## GNU General Public License for more details.
	16	##
	17	## You should have received a copy of the GNU General Public License
	18	## along with this program; if not, write to the Free Software
	19	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	##
	21
	22	# SPI protocol decoder
	23
	24	import sigrokdecode as srd
	25
	26	# Key: (CPOL, CPHA). Value: SPI mode.
	27	# Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
	28	# Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
	29	spi_mode = {
	30	(0, 0): 0, # Mode 0
	31	(0, 1): 1, # Mode 1
	32	(1, 0): 2, # Mode 2
	33	(1, 1): 3, # Mode 3
	34	}
	35
	36	class Decoder(srd.Decoder):
	37	api_version = 1
	38	id = 'spi'
	39	name = 'SPI'
	40	longname = 'Serial Peripheral Interface'
	41	desc = 'Full-duplex, synchronous, serial bus.'
	42	license = 'gplv2+'
	43	inputs = ['logic']
	44	outputs = ['spi']
	45	probes = [
	46	{'id': 'miso', 'name': 'MISO',
	47	'desc': 'SPI MISO line (Master in, slave out)'},
	48	{'id': 'mosi', 'name': 'MOSI',
	49	'desc': 'SPI MOSI line (Master out, slave in)'},
	50	{'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
	51	]
	52	optional_probes = [
	53	{'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'},
	54	]
	55	options = {
	56	'cs_polarity': ['CS# polarity', 'active-low'],
	57	'cpol': ['Clock polarity', 0],
	58	'cpha': ['Clock phase', 0],
	59	'bitorder': ['Bit order within the SPI data', 'msb-first'],
	60	'wordsize': ['Word size of SPI data', 8], # 1-64?
	61	'format': ['Data format', 'hex'],
	62	}
	63	annotations = [
	64	['MISO/MOSI data', 'MISO/MOSI SPI data'],
	65	['MISO data', 'MISO SPI data'],
	66	['MOSI data', 'MOSI SPI data'],
	67	['Warnings', 'Human-readable warnings'],
	68	]
	69
	70	def __init__(self):
	71	self.oldsck = 1
	72	self.bitcount = 0
	73	self.mosidata = 0
	74	self.misodata = 0
	75	self.bytesreceived = 0
	76	self.startsample = -1
	77	self.samplenum = -1
	78	self.cs_was_deasserted_during_data_word = 0
	79	self.oldcs = -1
	80	self.oldpins = None
	81	self.state = 'IDLE'
	82
	83	def start(self, metadata):
	84	self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
	85	self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
	86
	87	def report(self):
	88	return 'SPI: %d bytes received' % self.bytesreceived
	89
	90	def putpw(self, data):
	91	self.put(self.startsample, self.samplenum, self.out_proto, data)
	92
	93	def putw(self, data):
	94	self.put(self.startsample, self.samplenum, self.out_ann, data)
	95
	96	def handle_bit(self, miso, mosi, sck, cs):
	97	# If this is the first bit, save its sample number.
	98	if self.bitcount == 0:
	99	self.startsample = self.samplenum
	100	if self.have_cs:
	101	active_low = (self.options['cs_polarity'] == 'active-low')
	102	deasserted = cs if active_low else not cs
	103	if deasserted:
	104	self.cs_was_deasserted_during_data_word = 1
	105
	106	ws = self.options['wordsize']
	107
	108	# Receive MOSI bit into our shift register.
	109	if self.options['bitorder'] == 'msb-first':
	110	self.mosidata \|= mosi << (ws - 1 - self.bitcount)
	111	else:
	112	self.mosidata \|= mosi << self.bitcount
	113
	114	# Receive MISO bit into our shift register.
	115	if self.options['bitorder'] == 'msb-first':
	116	self.misodata \|= miso << (ws - 1 - self.bitcount)
	117	else:
	118	self.misodata \|= miso << self.bitcount
	119
	120	self.bitcount += 1
	121
	122	# Continue to receive if not enough bits were received, yet.
	123	if self.bitcount != ws:
	124	return
	125
	126	self.putpw(['DATA', self.mosidata, self.misodata])
	127	self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]])
	128	self.putw([1, ['%02X' % self.misodata]])
	129	self.putw([2, ['%02X' % self.mosidata]])
	130
	131	if self.cs_was_deasserted_during_data_word:
	132	self.putw([3, ['CS# was deasserted during this data word!']])
	133
	134	# Reset decoder state.
	135	self.mosidata = self.misodata = self.bitcount = 0
	136
	137	# Keep stats for summary.
	138	self.bytesreceived += 1
	139
	140	def find_clk_edge(self, miso, mosi, sck, cs):
	141	if self.have_cs and self.oldcs != cs:
	142	# Send all CS# pin value changes.
	143	self.put(self.samplenum, self.samplenum, self.out_proto,
	144	['CS-CHANGE', self.oldcs, cs])
	145	self.oldcs = cs
	146	# Reset decoder state when CS# changes (and the CS# pin is used).
	147	self.mosidata = self.misodata = self.bitcount= 0
	148
	149	# Ignore sample if the clock pin hasn't changed.
	150	if sck == self.oldsck:
	151	return
	152
	153	self.oldsck = sck
	154
	155	# Sample data on rising/falling clock edge (depends on mode).
	156	mode = spi_mode[self.options['cpol'], self.options['cpha']]
	157	if mode == 0 and sck == 0: # Sample on rising clock edge
	158	return
	159	elif mode == 1 and sck == 1: # Sample on falling clock edge
	160	return
	161	elif mode == 2 and sck == 1: # Sample on falling clock edge
	162	return
	163	elif mode == 3 and sck == 0: # Sample on rising clock edge
	164	return
	165
	166	# Found the correct clock edge, now get the SPI bit(s).
	167	self.handle_bit(miso, mosi, sck, cs)
	168
	169	def decode(self, ss, es, data):
	170	# TODO: Either MISO or MOSI could be optional. CS# is optional.
	171	for (self.samplenum, pins) in data:
	172
	173	# Ignore identical samples early on (for performance reasons).
	174	if self.oldpins == pins:
	175	continue
	176	self.oldpins, (miso, mosi, sck, cs) = pins, pins
	177	self.have_cs = (cs in (0, 1))
	178
	179	# State machine.
	180	if self.state == 'IDLE':
	181	self.find_clk_edge(miso, mosi, sck, cs)
	182	else:
	183	raise Exception('Invalid state: %s' % self.state)
	184