[libsigrokdecode.git] / decoders / spi / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

import sigrokdecode as srd

'''
Protocol output format:

SPI packet:
[<cmd>, <data1>, <data2>]

Commands:
 - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
   The data is _usually_ 8 bits (but can also be fewer or more bits).
   Both data items are Python numbers (not strings), or None if the respective
   probe was not supplied.
 - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
   Both data items are Python numbers (0/1), not strings.

Examples:
 ['CS-CHANGE', 1, 0]
 ['DATA', 0xff, 0x3a]
 ['DATA', 0x65, 0x00]
 ['DATA', 0xa8, None]
 ['DATA', None, 0x55]
 ['CS-CHANGE', 0, 1]
'''

# Key: (CPOL, CPHA). Value: SPI mode.
# Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
# Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
spi_mode = {
    (0, 0): 0, # Mode 0
    (0, 1): 1, # Mode 1
    (1, 0): 2, # Mode 2
    (1, 1): 3, # Mode 3
}

class Decoder(srd.Decoder):
    api_version = 1
    id = 'spi'
    name = 'SPI'
    longname = 'Serial Peripheral Interface'
    desc = 'Full-duplex, synchronous, serial bus.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['spi']
    probes = [
        {'id': 'clk', 'name': 'CLK', 'desc': 'SPI clock line'},
    ]
    optional_probes = [
        {'id': 'miso', 'name': 'MISO',
         'desc': 'SPI MISO line (master in, slave out)'},
        {'id': 'mosi', 'name': 'MOSI',
         'desc': 'SPI MOSI line (master out, slave in)'},
        {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'},
    ]
    options = {
        'cs_polarity': ['CS# polarity', 'active-low'],
        'cpol': ['Clock polarity', 0],
        'cpha': ['Clock phase', 0],
        'bitorder': ['Bit order within the SPI data', 'msb-first'],
        'wordsize': ['Word size of SPI data', 8], # 1-64?
        'format': ['Data format', 'hex'],
    }
    annotations = [
        ['miso-data', 'MISO SPI data'],
        ['mosi-data', 'MOSI SPI data'],
        ['warnings', 'Human-readable warnings'],
    ]

    def __init__(self):
        self.samplerate = None
        self.oldclk = 1
        self.bitcount = 0
        self.mosidata = 0
        self.misodata = 0
        self.startsample = -1
        self.samplenum = -1
        self.cs_was_deasserted_during_data_word = 0
        self.oldcs = -1
        self.oldpins = None
        self.have_cs = None
        self.have_miso = None
        self.have_mosi = None
        self.state = 'IDLE'

    def metadata(self, key, value):
        if key == srd.SRD_CONF_SAMPLERATE:
            self.samplerate = value

    def start(self):
        self.out_proto = self.register(srd.OUTPUT_PYTHON)
        self.out_ann = self.register(srd.OUTPUT_ANN)
        self.out_bitrate = self.register(srd.OUTPUT_META,
                meta=(int, 'Bitrate', 'Bitrate during transfers'))

    def putpw(self, data):
        self.put(self.startsample, self.samplenum, self.out_proto, data)

    def putw(self, data):
        self.put(self.startsample, self.samplenum, self.out_ann, data)

    def handle_bit(self, miso, mosi, clk, cs):
        # If this is the first bit, save its sample number.
        if self.bitcount == 0:
            self.startsample = self.samplenum
            if self.have_cs:
                active_low = (self.options['cs_polarity'] == 'active-low')
                deasserted = cs if active_low else not cs
                if deasserted:
                    self.cs_was_deasserted_during_data_word = 1

        ws = self.options['wordsize']

        # Receive MOSI bit into our shift register.
        if self.have_mosi:
            if self.options['bitorder'] == 'msb-first':
                self.mosidata |= mosi << (ws - 1 - self.bitcount)
            else:
                self.mosidata |= mosi << self.bitcount

        # Receive MISO bit into our shift register.
        if self.have_miso:
            if self.options['bitorder'] == 'msb-first':
                self.misodata |= miso << (ws - 1 - self.bitcount)
            else:
                self.misodata |= miso << self.bitcount

        self.bitcount += 1

        # Continue to receive if not enough bits were received, yet.
        if self.bitcount != ws:
            return

        si = self.mosidata if self.have_mosi else None
        so = self.misodata if self.have_miso else None

        # Pass MOSI and MISO to the next PD up the stack.
        self.putpw(['DATA', si, so])

        # Annotations.
        if self.have_miso:
            self.putw([0, ['%02X' % self.misodata]])
        if self.have_mosi:
            self.putw([1, ['%02X' % self.mosidata]])

        # Meta bitrate.
        elapsed = 1 / float(self.samplerate) * (self.samplenum - self.startsample + 1)
        bitrate = int(1 / elapsed * self.options['wordsize'])
        self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)

        if self.have_cs and self.cs_was_deasserted_during_data_word:
            self.putw([2, ['CS# was deasserted during this data word!']])

        # Reset decoder state.
        self.misodata = 0 if self.have_miso else None
        self.mosidata = 0 if self.have_mosi else None
        self.bitcount = 0

    def find_clk_edge(self, miso, mosi, clk, cs):
        if self.have_cs and self.oldcs != cs:
            # Send all CS# pin value changes.
            self.put(self.samplenum, self.samplenum, self.out_proto,
                     ['CS-CHANGE', self.oldcs, cs])
            self.oldcs = cs
            # Reset decoder state when CS# changes (and the CS# pin is used).
            self.misodata = 0 if self.have_miso else None
            self.mosidata = 0 if self.have_mosi else None
            self.bitcount = 0

        # Ignore sample if the clock pin hasn't changed.
        if clk == self.oldclk:
            return

        self.oldclk = clk

        # Sample data on rising/falling clock edge (depends on mode).
        mode = spi_mode[self.options['cpol'], self.options['cpha']]
        if mode == 0 and clk == 0:   # Sample on rising clock edge
            return
        elif mode == 1 and clk == 1: # Sample on falling clock edge
            return
        elif mode == 2 and clk == 1: # Sample on falling clock edge
            return
        elif mode == 3 and clk == 0: # Sample on rising clock edge
            return

        # Found the correct clock edge, now get the SPI bit(s).
        self.handle_bit(miso, mosi, clk, cs)

    def decode(self, ss, es, data):
        if self.samplerate is None:
            raise Exception("Cannot decode without samplerate.")
        # Either MISO or MOSI can be omitted (but not both). CS# is optional.
        for (self.samplenum, pins) in data:

            # Ignore identical samples early on (for performance reasons).
            if self.oldpins == pins:
                continue
            self.oldpins, (clk, miso, mosi, cs) = pins, pins
            self.have_miso = (miso in (0, 1))
            self.have_mosi = (mosi in (0, 1))
            self.have_cs = (cs in (0, 1))

            # State machine.
            if self.state == 'IDLE':
                self.find_clk_edge(miso, mosi, clk, cs)
            else:
                raise Exception('Invalid state: %s' % self.state)
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
	5	## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
	6	##
	7	## This program is free software; you can redistribute it and/or modify
	8	## it under the terms of the GNU General Public License as published by
	9	## the Free Software Foundation; either version 2 of the License, or
	10	## (at your option) any later version.
	11	##
	12	## This program is distributed in the hope that it will be useful,
	13	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	## GNU General Public License for more details.
	16	##
	17	## You should have received a copy of the GNU General Public License
	18	## along with this program; if not, write to the Free Software
	19	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	##
	21
	22	import sigrokdecode as srd
	23
	24	'''
	25	Protocol output format:
	26
	27	SPI packet:
	28	[<cmd>, <data1>, <data2>]
	29
	30	Commands:
	31	- 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
	32	The data is _usually_ 8 bits (but can also be fewer or more bits).
	33	Both data items are Python numbers (not strings), or None if the respective
	34	probe was not supplied.
	35	- 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
	36	Both data items are Python numbers (0/1), not strings.
	37
	38	Examples:
	39	['CS-CHANGE', 1, 0]
	40	['DATA', 0xff, 0x3a]
	41	['DATA', 0x65, 0x00]
	42	['DATA', 0xa8, None]
	43	['DATA', None, 0x55]
	44	['CS-CHANGE', 0, 1]
	45	'''
	46
	47	# Key: (CPOL, CPHA). Value: SPI mode.
	48	# Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
	49	# Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
	50	spi_mode = {
	51	(0, 0): 0, # Mode 0
	52	(0, 1): 1, # Mode 1
	53	(1, 0): 2, # Mode 2
	54	(1, 1): 3, # Mode 3
	55	}
	56
	57	class Decoder(srd.Decoder):
	58	api_version = 1
	59	id = 'spi'
	60	name = 'SPI'
	61	longname = 'Serial Peripheral Interface'
	62	desc = 'Full-duplex, synchronous, serial bus.'
	63	license = 'gplv2+'
	64	inputs = ['logic']
	65	outputs = ['spi']
	66	probes = [
	67	{'id': 'clk', 'name': 'CLK', 'desc': 'SPI clock line'},
	68	]
	69	optional_probes = [
	70	{'id': 'miso', 'name': 'MISO',
	71	'desc': 'SPI MISO line (master in, slave out)'},
	72	{'id': 'mosi', 'name': 'MOSI',
	73	'desc': 'SPI MOSI line (master out, slave in)'},
	74	{'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'},
	75	]
	76	options = {
	77	'cs_polarity': ['CS# polarity', 'active-low'],
	78	'cpol': ['Clock polarity', 0],
	79	'cpha': ['Clock phase', 0],
	80	'bitorder': ['Bit order within the SPI data', 'msb-first'],
	81	'wordsize': ['Word size of SPI data', 8], # 1-64?
	82	'format': ['Data format', 'hex'],
	83	}
	84	annotations = [
	85	['miso-data', 'MISO SPI data'],
	86	['mosi-data', 'MOSI SPI data'],
	87	['warnings', 'Human-readable warnings'],
	88	]
	89
	90	def __init__(self):
	91	self.samplerate = None
	92	self.oldclk = 1
	93	self.bitcount = 0
	94	self.mosidata = 0
	95	self.misodata = 0
	96	self.startsample = -1
	97	self.samplenum = -1
	98	self.cs_was_deasserted_during_data_word = 0
	99	self.oldcs = -1
	100	self.oldpins = None
	101	self.have_cs = None
	102	self.have_miso = None
	103	self.have_mosi = None
	104	self.state = 'IDLE'
	105
	106	def metadata(self, key, value):
	107	if key == srd.SRD_CONF_SAMPLERATE:
	108	self.samplerate = value
	109
	110	def start(self):
	111	self.out_proto = self.register(srd.OUTPUT_PYTHON)
	112	self.out_ann = self.register(srd.OUTPUT_ANN)
	113	self.out_bitrate = self.register(srd.OUTPUT_META,
	114	meta=(int, 'Bitrate', 'Bitrate during transfers'))
	115
	116	def putpw(self, data):
	117	self.put(self.startsample, self.samplenum, self.out_proto, data)
	118
	119	def putw(self, data):
	120	self.put(self.startsample, self.samplenum, self.out_ann, data)
	121
	122	def handle_bit(self, miso, mosi, clk, cs):
	123	# If this is the first bit, save its sample number.
	124	if self.bitcount == 0:
	125	self.startsample = self.samplenum
	126	if self.have_cs:
	127	active_low = (self.options['cs_polarity'] == 'active-low')
	128	deasserted = cs if active_low else not cs
	129	if deasserted:
	130	self.cs_was_deasserted_during_data_word = 1
	131
	132	ws = self.options['wordsize']
	133
	134	# Receive MOSI bit into our shift register.
	135	if self.have_mosi:
	136	if self.options['bitorder'] == 'msb-first':
	137	self.mosidata \|= mosi << (ws - 1 - self.bitcount)
	138	else:
	139	self.mosidata \|= mosi << self.bitcount
	140
	141	# Receive MISO bit into our shift register.
	142	if self.have_miso:
	143	if self.options['bitorder'] == 'msb-first':
	144	self.misodata \|= miso << (ws - 1 - self.bitcount)
	145	else:
	146	self.misodata \|= miso << self.bitcount
	147
	148	self.bitcount += 1
	149
	150	# Continue to receive if not enough bits were received, yet.
	151	if self.bitcount != ws:
	152	return
	153
	154	si = self.mosidata if self.have_mosi else None
	155	so = self.misodata if self.have_miso else None
	156
	157	# Pass MOSI and MISO to the next PD up the stack.
	158	self.putpw(['DATA', si, so])
	159
	160	# Annotations.
	161	if self.have_miso:
	162	self.putw([0, ['%02X' % self.misodata]])
	163	if self.have_mosi:
	164	self.putw([1, ['%02X' % self.mosidata]])
	165
	166	# Meta bitrate.
	167	elapsed = 1 / float(self.samplerate) * (self.samplenum - self.startsample + 1)
	168	bitrate = int(1 / elapsed * self.options['wordsize'])
	169	self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)
	170
	171	if self.have_cs and self.cs_was_deasserted_during_data_word:
	172	self.putw([2, ['CS# was deasserted during this data word!']])
	173
	174	# Reset decoder state.
	175	self.misodata = 0 if self.have_miso else None
	176	self.mosidata = 0 if self.have_mosi else None
	177	self.bitcount = 0
	178
	179	def find_clk_edge(self, miso, mosi, clk, cs):
	180	if self.have_cs and self.oldcs != cs:
	181	# Send all CS# pin value changes.
	182	self.put(self.samplenum, self.samplenum, self.out_proto,
	183	['CS-CHANGE', self.oldcs, cs])
	184	self.oldcs = cs
	185	# Reset decoder state when CS# changes (and the CS# pin is used).
	186	self.misodata = 0 if self.have_miso else None
	187	self.mosidata = 0 if self.have_mosi else None
	188	self.bitcount = 0
	189
	190	# Ignore sample if the clock pin hasn't changed.
	191	if clk == self.oldclk:
	192	return
	193
	194	self.oldclk = clk
	195
	196	# Sample data on rising/falling clock edge (depends on mode).
	197	mode = spi_mode[self.options['cpol'], self.options['cpha']]
	198	if mode == 0 and clk == 0: # Sample on rising clock edge
	199	return
	200	elif mode == 1 and clk == 1: # Sample on falling clock edge
	201	return
	202	elif mode == 2 and clk == 1: # Sample on falling clock edge
	203	return
	204	elif mode == 3 and clk == 0: # Sample on rising clock edge
	205	return
	206
	207	# Found the correct clock edge, now get the SPI bit(s).
	208	self.handle_bit(miso, mosi, clk, cs)
	209
	210	def decode(self, ss, es, data):
	211	if self.samplerate is None:
	212	raise Exception("Cannot decode without samplerate.")
	213	# Either MISO or MOSI can be omitted (but not both). CS# is optional.
	214	for (self.samplenum, pins) in data:
	215
	216	# Ignore identical samples early on (for performance reasons).
	217	if self.oldpins == pins:
	218	continue
	219	self.oldpins, (clk, miso, mosi, cs) = pins, pins
	220	self.have_miso = (miso in (0, 1))
	221	self.have_mosi = (mosi in (0, 1))
	222	self.have_cs = (cs in (0, 1))
	223
	224	# State machine.
	225	if self.state == 'IDLE':
	226	self.find_clk_edge(miso, mosi, clk, cs)
	227	else:
	228	raise Exception('Invalid state: %s' % self.state)
	229