[libsigrokdecode.git] / decoders / spi / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# SPI protocol decoder

import sigrokdecode as srd

# Key: (CPOL, CPHA). Value: SPI mode.
# Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
# Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
spi_mode = {
    (0, 0): 0, # Mode 0
    (0, 1): 1, # Mode 1
    (1, 0): 2, # Mode 2
    (1, 1): 3, # Mode 3
}

class Decoder(srd.Decoder):
    api_version = 1
    id = 'spi'
    name = 'SPI'
    longname = 'Serial Peripheral Interface'
    desc = 'Full-duplex, synchronous, serial bus.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['spi']
    probes = [
        {'id': 'miso', 'name': 'MISO',
         'desc': 'SPI MISO line (Master in, slave out)'},
        {'id': 'mosi', 'name': 'MOSI',
         'desc': 'SPI MOSI line (Master out, slave in)'},
        {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
        {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
    ]
    optional_probes = [] # TODO
    options = {
        'cs_polarity': ['CS# polarity', 'active-low'],
        'cpol': ['Clock polarity', 0],
        'cpha': ['Clock phase', 0],
        'bitorder': ['Bit order within the SPI data', 'msb-first'],
        'wordsize': ['Word size of SPI data', 8], # 1-64?
        'format': ['Data format', 'hex'],
    }
    annotations = [
        ['Data', 'SPI data'],
        ['Warnings', 'Human-readable warnings'],
    ]

    def __init__(self):
        self.oldsck = 1
        self.bitcount = 0
        self.mosidata = 0
        self.misodata = 0
        self.bytesreceived = 0
        self.samplenum = -1
        self.cs_was_deasserted_during_data_word = 0
        self.oldcs = -1
        self.oldpins = None

    def start(self, metadata):
        self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
        self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')

    def report(self):
        return 'SPI: %d bytes received' % self.bytesreceived

    def decode(self, ss, es, data):
        # TODO: Either MISO or MOSI could be optional. CS# is optional.
        for (self.samplenum, pins) in data:

            # Ignore identical samples early on (for performance reasons).
            if self.oldpins == pins:
                continue
            self.oldpins, (miso, mosi, sck, cs) = pins, pins

            if self.oldcs != cs:
                # Send all CS# pin value changes.
                self.put(self.samplenum, self.samplenum, self.out_proto,
                         ['CS-CHANGE', self.oldcs, cs])
                self.put(self.samplenum, self.samplenum, self.out_ann,
                         [0, ['CS-CHANGE: %d->%d' % (self.oldcs, cs)]])
                self.oldcs = cs

            # Ignore sample if the clock pin hasn't changed.
            if sck == self.oldsck:
                continue

            self.oldsck = sck

            # Sample data on rising/falling clock edge (depends on mode).
            mode = spi_mode[self.options['cpol'], self.options['cpha']]
            if mode == 0 and sck == 0:   # Sample on rising clock edge
                    continue
            elif mode == 1 and sck == 1: # Sample on falling clock edge
                    continue
            elif mode == 2 and sck == 1: # Sample on falling clock edge
                    continue
            elif mode == 3 and sck == 0: # Sample on rising clock edge
                    continue

            # If this is the first bit, save its sample number.
            if self.bitcount == 0:
                self.start_sample = self.samplenum
                active_low = (self.options['cs_polarity'] == 'active-low')
                deasserted = cs if active_low else not cs
                if deasserted:
                    self.cs_was_deasserted_during_data_word = 1

            ws = self.options['wordsize']

            # Receive MOSI bit into our shift register.
            if self.options['bitorder'] == 'msb-first':
                self.mosidata |= mosi << (ws - 1 - self.bitcount)
            else:
                self.mosidata |= mosi << self.bitcount

            # Receive MISO bit into our shift register.
            if self.options['bitorder'] == 'msb-first':
                self.misodata |= miso << (ws - 1 - self.bitcount)
            else:
                self.misodata |= miso << self.bitcount

            self.bitcount += 1

            # Continue to receive if not enough bits were received, yet.
            if self.bitcount != ws:
                continue

            self.put(self.start_sample, self.samplenum, self.out_proto,
                     ['DATA', self.mosidata, self.misodata])
            self.put(self.start_sample, self.samplenum, self.out_ann,
                     [0, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
                     self.misodata)]])

            if self.cs_was_deasserted_during_data_word:
                self.put(self.start_sample, self.samplenum, self.out_ann,
                         [1, ['CS# was deasserted during this '
                         'SPI data byte!']])

            # Reset decoder state.
            self.mosidata = 0
            self.misodata = 0
            self.bitcount = 0

            # Keep stats for summary.
            self.bytesreceived += 1
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
	5	## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
	6	##
	7	## This program is free software; you can redistribute it and/or modify
	8	## it under the terms of the GNU General Public License as published by
	9	## the Free Software Foundation; either version 2 of the License, or
	10	## (at your option) any later version.
	11	##
	12	## This program is distributed in the hope that it will be useful,
	13	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	## GNU General Public License for more details.
	16	##
	17	## You should have received a copy of the GNU General Public License
	18	## along with this program; if not, write to the Free Software
	19	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	##
	21
	22	# SPI protocol decoder
	23
	24	import sigrokdecode as srd
	25
	26	# Key: (CPOL, CPHA). Value: SPI mode.
	27	# Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
	28	# Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
	29	spi_mode = {
	30	(0, 0): 0, # Mode 0
	31	(0, 1): 1, # Mode 1
	32	(1, 0): 2, # Mode 2
	33	(1, 1): 3, # Mode 3
	34	}
	35
	36	class Decoder(srd.Decoder):
	37	api_version = 1
	38	id = 'spi'
	39	name = 'SPI'
	40	longname = 'Serial Peripheral Interface'
	41	desc = 'Full-duplex, synchronous, serial bus.'
	42	license = 'gplv2+'
	43	inputs = ['logic']
	44	outputs = ['spi']
	45	probes = [
	46	{'id': 'miso', 'name': 'MISO',
	47	'desc': 'SPI MISO line (Master in, slave out)'},
	48	{'id': 'mosi', 'name': 'MOSI',
	49	'desc': 'SPI MOSI line (Master out, slave in)'},
	50	{'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
	51	{'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
	52	]
	53	optional_probes = [] # TODO
	54	options = {
	55	'cs_polarity': ['CS# polarity', 'active-low'],
	56	'cpol': ['Clock polarity', 0],
	57	'cpha': ['Clock phase', 0],
	58	'bitorder': ['Bit order within the SPI data', 'msb-first'],
	59	'wordsize': ['Word size of SPI data', 8], # 1-64?
	60	'format': ['Data format', 'hex'],
	61	}
	62	annotations = [
	63	['Data', 'SPI data'],
	64	['Warnings', 'Human-readable warnings'],
	65	]
	66
	67	def __init__(self):
	68	self.oldsck = 1
	69	self.bitcount = 0
	70	self.mosidata = 0
	71	self.misodata = 0
	72	self.bytesreceived = 0
	73	self.samplenum = -1
	74	self.cs_was_deasserted_during_data_word = 0
	75	self.oldcs = -1
	76	self.oldpins = None
	77
	78	def start(self, metadata):
	79	self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
	80	self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
	81
	82	def report(self):
	83	return 'SPI: %d bytes received' % self.bytesreceived
	84
	85	def decode(self, ss, es, data):
	86	# TODO: Either MISO or MOSI could be optional. CS# is optional.
	87	for (self.samplenum, pins) in data:
	88
	89	# Ignore identical samples early on (for performance reasons).
	90	if self.oldpins == pins:
	91	continue
	92	self.oldpins, (miso, mosi, sck, cs) = pins, pins
	93
	94	if self.oldcs != cs:
	95	# Send all CS# pin value changes.
	96	self.put(self.samplenum, self.samplenum, self.out_proto,
	97	['CS-CHANGE', self.oldcs, cs])
	98	self.put(self.samplenum, self.samplenum, self.out_ann,
	99	[0, ['CS-CHANGE: %d->%d' % (self.oldcs, cs)]])
	100	self.oldcs = cs
	101
	102	# Ignore sample if the clock pin hasn't changed.
	103	if sck == self.oldsck:
	104	continue
	105
	106	self.oldsck = sck
	107
	108	# Sample data on rising/falling clock edge (depends on mode).
	109	mode = spi_mode[self.options['cpol'], self.options['cpha']]
	110	if mode == 0 and sck == 0: # Sample on rising clock edge
	111	continue
	112	elif mode == 1 and sck == 1: # Sample on falling clock edge
	113	continue
	114	elif mode == 2 and sck == 1: # Sample on falling clock edge
	115	continue
	116	elif mode == 3 and sck == 0: # Sample on rising clock edge
	117	continue
	118
	119	# If this is the first bit, save its sample number.
	120	if self.bitcount == 0:
	121	self.start_sample = self.samplenum
	122	active_low = (self.options['cs_polarity'] == 'active-low')
	123	deasserted = cs if active_low else not cs
	124	if deasserted:
	125	self.cs_was_deasserted_during_data_word = 1
	126
	127	ws = self.options['wordsize']
	128
	129	# Receive MOSI bit into our shift register.
	130	if self.options['bitorder'] == 'msb-first':
	131	self.mosidata \|= mosi << (ws - 1 - self.bitcount)
	132	else:
	133	self.mosidata \|= mosi << self.bitcount
	134
	135	# Receive MISO bit into our shift register.
	136	if self.options['bitorder'] == 'msb-first':
	137	self.misodata \|= miso << (ws - 1 - self.bitcount)
	138	else:
	139	self.misodata \|= miso << self.bitcount
	140
	141	self.bitcount += 1
	142
	143	# Continue to receive if not enough bits were received, yet.
	144	if self.bitcount != ws:
	145	continue
	146
	147	self.put(self.start_sample, self.samplenum, self.out_proto,
	148	['DATA', self.mosidata, self.misodata])
	149	self.put(self.start_sample, self.samplenum, self.out_ann,
	150	[0, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
	151	self.misodata)]])
	152
	153	if self.cs_was_deasserted_during_data_word:
	154	self.put(self.start_sample, self.samplenum, self.out_ann,
	155	[1, ['CS# was deasserted during this '
	156	'SPI data byte!']])
	157
	158	# Reset decoder state.
	159	self.mosidata = 0
	160	self.misodata = 0
	161	self.bitcount = 0
	162
	163	# Keep stats for summary.
	164	self.bytesreceived += 1
	165