]>
Commit | Line | Data |
---|---|---|
1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2015 Josef Gajdusek <atx@atx.name> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | ## | |
19 | ||
20 | import sigrokdecode as srd | |
21 | import operator | |
22 | import collections | |
23 | from functools import reduce | |
24 | ||
25 | end_codes = ( | |
26 | 'Unknown', | |
27 | 'Charge Complete', | |
28 | 'Internal Fault', | |
29 | 'Over Temperature', | |
30 | 'Over Voltage', | |
31 | 'Over Current', | |
32 | 'Battery Failure', | |
33 | 'Reconfigure', | |
34 | 'No Response', | |
35 | ) | |
36 | ||
37 | class SamplerateError(Exception): | |
38 | pass | |
39 | ||
40 | def calc_checksum(packet): | |
41 | return reduce(operator.xor, packet[:-1]) | |
42 | ||
43 | def bits_to_uint(bits): | |
44 | # LSB first | |
45 | return reduce(lambda i, v: (i >> 1) | (v << (len(bits) - 1)), bits, 0) | |
46 | ||
47 | class Decoder(srd.Decoder): | |
48 | api_version = 3 | |
49 | id = 'qi' | |
50 | name = 'Qi' | |
51 | longname = 'Qi charger protocol' | |
52 | desc = 'Protocol used by Qi receiver.' | |
53 | license = 'gplv2+' | |
54 | inputs = ['logic'] | |
55 | outputs = ['qi'] | |
56 | channels = ( | |
57 | {'id': 'qi', 'name': 'Qi', 'desc': 'Demodulated Qi data line'}, | |
58 | ) | |
59 | annotations = ( | |
60 | ('bits', 'Bits'), | |
61 | ('bytes-errors', 'Bit errors'), | |
62 | ('bytes-start', 'Start bits'), | |
63 | ('bytes-info', 'Info bits'), | |
64 | ('bytes-data', 'Data bytes'), | |
65 | ('packets-data', 'Packet data'), | |
66 | ('packets-checksum-ok', 'Packet checksum'), | |
67 | ('packets-checksum-err', 'Packet checksum'), | |
68 | ) | |
69 | annotation_rows = ( | |
70 | ('bits', 'Bits', (0,)), | |
71 | ('bytes', 'Bytes', (1, 2, 3, 4)), | |
72 | ('packets', 'Packets', (5, 6, 7)), | |
73 | ) | |
74 | ||
75 | def __init__(self): | |
76 | self.reset() | |
77 | ||
78 | def reset(self): | |
79 | self.samplerate = None | |
80 | self.reset_variables() | |
81 | ||
82 | def reset_variables(self): | |
83 | self.counter = 0 | |
84 | self.prev = None | |
85 | self.state = 'IDLE' | |
86 | self.lastbit = 0 | |
87 | self.bytestart = 0 | |
88 | self.deq = collections.deque(maxlen = 2) | |
89 | self.bits = [] | |
90 | self.bitsi = [0] | |
91 | self.bytesi = [] | |
92 | self.packet = [] | |
93 | ||
94 | def metadata(self, key, value): | |
95 | if key == srd.SRD_CONF_SAMPLERATE: | |
96 | self.samplerate = value | |
97 | self.bit_width = float(self.samplerate) / 2e3 | |
98 | ||
99 | def start(self): | |
100 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
101 | self.reset_variables() | |
102 | ||
103 | def packet_len(self, byte): | |
104 | if 0x00 <= byte <= 0x1f: | |
105 | return int(1 + (byte - 0) / 32) | |
106 | if 0x20 <= byte <= 0x7f: | |
107 | return int(2 + (byte - 32) / 16) | |
108 | if 0x80 <= byte <= 0xdf: | |
109 | return int(8 + (byte - 128) / 8) | |
110 | if 0xe0 <= byte <= 0xff: | |
111 | return int(20 + (byte - 224) / 4) | |
112 | ||
113 | def in_tolerance(self, l): | |
114 | return (0.75 * self.bit_width) < l < (1.25 * self.bit_width) | |
115 | ||
116 | def putp(self, data): | |
117 | self.put(self.bytesi[0], self.bytesi[-1], self.out_ann, [5, data]) | |
118 | ||
119 | def process_packet(self): | |
120 | if self.packet[0] == 0x01: # Signal Strength | |
121 | self.putp(['Signal Strength: %d' % self.packet[1], | |
122 | 'SS: %d' % self.packet[1], 'SS']) | |
123 | elif self.packet[0] == 0x02: # End Power Transfer | |
124 | reason = end_codes[self.packet[1]] if self.packet[1] < len(end_codes) else 'Reserved' | |
125 | self.putp(['End Power Transfer: %s' % reason, | |
126 | 'EPT: %s' % reason, 'EPT']) | |
127 | elif self.packet[0] == 0x03: # Control Error | |
128 | val = self.packet[1] if self.packet[1] < 128 else (self.packet[1] & 0x7f) - 128 | |
129 | self.putp(['Control Error: %d' % val, 'CE: %d' % val, 'CE']) | |
130 | elif self.packet[0] == 0x04: # Received Power | |
131 | self.putp(['Received Power: %d' % self.packet[1], | |
132 | 'RP: %d' % self.packet[1], 'RP']) | |
133 | elif self.packet[0] == 0x05: # Charge Status | |
134 | self.putp(['Charge Status: %d' % self.packet[1], | |
135 | 'CS: %d' % self.packet[1], 'CS']) | |
136 | elif self.packet[0] == 0x06: # Power Control Hold-off | |
137 | self.putp(['Power Control Hold-off: %dms' % self.packet[1], | |
138 | 'PCH: %d' % self.packet[1]], 'PCH') | |
139 | elif self.packet[0] == 0x51: # Configuration | |
140 | powerclass = (self.packet[1] & 0xc0) >> 7 | |
141 | maxpower = self.packet[1] & 0x3f | |
142 | prop = (self.packet[3] & 0x80) >> 7 | |
143 | count = self.packet[3] & 0x07 | |
144 | winsize = (self.packet[4] & 0xf8) >> 3 | |
145 | winoff = self.packet[4] & 0x07 | |
146 | self.putp(['Configuration: Power Class = %d, Maximum Power = %d, Prop = %d,' | |
147 | 'Count = %d, Window Size = %d, Window Offset = %d' % | |
148 | (powerclass, maxpower, prop, count, winsize, winoff), | |
149 | 'C: PC = %d MP = %d P = %d C = %d WS = %d WO = %d' % | |
150 | (powerclass, maxpower, prop, count, winsize, winoff), | |
151 | 'Configuration', 'C']) | |
152 | elif self.packet[0] == 0x71: # Identification | |
153 | version = '%d.%d' % ((self.packet[1] & 0xf0) >> 4, self.packet[1] & 0x0f) | |
154 | mancode = '%02x%02x' % (self.packet[2], self.packet[3]) | |
155 | devid = '%02x%02x%02x%02x' % (self.packet[4] & ~0x80, | |
156 | self.packet[5], self.packet[6], self.packet[7]) | |
157 | self.putp(['Identification: Version = %s, Manufacturer = %s, ' \ | |
158 | 'Device = %s' % (version, mancode, devid), | |
159 | 'ID: %s %s %s' % (version, mancode, devid), 'ID']) | |
160 | elif self.packet[0] == 0x81: # Extended Identification | |
161 | edevid = '%02x%02x%02x%02x%02x%02x%02x%02x' % self.packet[1:-1] | |
162 | self.putp(['Extended Identification: %s' % edevid, | |
163 | 'EI: %s' % edevid, 'EI']) | |
164 | elif self.packet[0] in (0x18, 0x19, 0x28, 0x29, 0x38, 0x48, 0x58, 0x68, | |
165 | 0x78, 0x85, 0xa4, 0xc4, 0xe2): # Proprietary | |
166 | self.putp(['Proprietary', 'P']) | |
167 | else: # Unknown | |
168 | self.putp(['Unknown', '?']) | |
169 | self.put(self.bytesi[-1], self.samplenum, self.out_ann, | |
170 | [6, ['Checksum OK', 'OK']] if \ | |
171 | calc_checksum(self.packet) == self.packet[-1] | |
172 | else [6, ['Checksum error', 'ERR']]) | |
173 | ||
174 | def process_byte(self): | |
175 | self.put(self.bytestart, self.bitsi[0], self.out_ann, | |
176 | ([2, ['Start bit', 'Start', 'S']]) if self.bits[0] == 0 else | |
177 | ([1, ['Start error', 'Start err', 'SE']])) | |
178 | databits = self.bits[1:9] | |
179 | data = bits_to_uint(databits) | |
180 | parity = reduce(lambda i, v: (i + v) % 2, databits, 1) | |
181 | self.put(self.bitsi[0], self.bitsi[8], self.out_ann, [4, ['%02x' % data]]) | |
182 | self.put(self.bitsi[8], self.bitsi[9], self.out_ann, | |
183 | ([3, ['Parity bit', 'Parity', 'P']]) if self.bits[9] == parity else | |
184 | ([1, ['Parity error', 'Parity err', 'PE']])) | |
185 | self.put(self.bitsi[9], self.bitsi[10], self.out_ann, | |
186 | ([3, ['Stop bit', 'Stop', 'S']]) if self.bits[10] == 1 else | |
187 | ([1, ['Stop error', 'Stop err', 'SE']])) | |
188 | ||
189 | self.bytesi.append(self.bytestart) | |
190 | self.packet.append(data) | |
191 | if self.packet_len(self.packet[0]) + 2 == len(self.packet): | |
192 | self.process_packet() | |
193 | self.bytesi.clear() | |
194 | self.packet.clear() | |
195 | ||
196 | def add_bit(self, bit): | |
197 | self.bits.append(bit) | |
198 | self.bitsi.append(self.samplenum) | |
199 | ||
200 | if self.state == 'IDLE' and len(self.bits) >= 5 and \ | |
201 | self.bits[-5:] == [1, 1, 1, 1, 0]: | |
202 | self.state = 'DATA' | |
203 | self.bytestart = self.bitsi[-2] | |
204 | self.bits = [0] | |
205 | self.bitsi = [self.samplenum] | |
206 | self.packet.clear() | |
207 | elif self.state == 'DATA' and len(self.bits) == 11: | |
208 | self.process_byte() | |
209 | self.bytestart = self.samplenum | |
210 | self.bits.clear() | |
211 | self.bitsi.clear() | |
212 | if self.state != 'IDLE': | |
213 | self.put(self.lastbit, self.samplenum, self.out_ann, [0, ['%d' % bit]]) | |
214 | self.lastbit = self.samplenum | |
215 | ||
216 | def handle_transition(self, l, htl): | |
217 | self.deq.append(l) | |
218 | if len(self.deq) >= 2 and \ | |
219 | (self.in_tolerance(self.deq[-1] + self.deq[-2]) or \ | |
220 | htl and self.in_tolerance(l * 2) and \ | |
221 | self.deq[-2] > 1.25 * self.bit_width): | |
222 | self.add_bit(1) | |
223 | self.deq.clear() | |
224 | elif self.in_tolerance(l): | |
225 | self.add_bit(0) | |
226 | self.deq.clear() | |
227 | elif l > (1.25 * self.bit_width): | |
228 | self.state = 'IDLE' | |
229 | self.bytesi.clear() | |
230 | self.packet.clear() | |
231 | self.bits.clear() | |
232 | self.bitsi.clear() | |
233 | ||
234 | def decode(self): | |
235 | if not self.samplerate: | |
236 | raise SamplerateError('Cannot decode without samplerate.') | |
237 | ||
238 | (qi,) = self.wait() | |
239 | self.handle_transition(self.samplenum, qi == 0) | |
240 | while True: | |
241 | prev = self.samplenum | |
242 | (qi,) = self.wait({0: 'e'}) | |
243 | self.handle_transition(self.samplenum - prev, qi == 0) |