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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2013 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | # Parallel (sync) bus protocol decoder | |
22 | ||
23 | import sigrokdecode as srd | |
24 | ||
25 | ''' | |
26 | Protocol output format: | |
27 | ||
28 | Packet: | |
29 | [<ptype>, <pdata>] | |
30 | ||
31 | <ptype>, <pdata> | |
32 | - 'ITEM', [<item>, <itembitsize>] | |
33 | - 'WORD', [<word>, <wordbitsize>, <worditemcount>] | |
34 | ||
35 | <item>: | |
36 | - A single item (a number). It can be of arbitrary size. The max. number | |
37 | of bits in this item is specified in <itembitsize>. | |
38 | ||
39 | <itembitsize>: | |
40 | - The size of an item (in bits). For a 4-bit parallel bus this is 4, | |
41 | for a 16-bit parallel bus this is 16, and so on. | |
42 | ||
43 | <word>: | |
44 | - A single word (a number). It can be of arbitrary size. The max. number | |
45 | of bits in this word is specified in <wordbitsize>. The (exact) number | |
46 | of items in this word is specified in <worditemcount>. | |
47 | ||
48 | <wordbitsize>: | |
49 | - The size of a word (in bits). For a 2-item word with 8-bit items | |
50 | <wordbitsize> is 16, for a 3-item word with 4-bit items <wordbitsize> | |
51 | is 12, and so on. | |
52 | ||
53 | <worditemcount>: | |
54 | - The size of a word (in number of items). For a 4-item word (no matter | |
55 | how many bits each item consists of) <worditemcount> is 4, for a 7-item | |
56 | word <worditemcount> is 7, and so on. | |
57 | ''' | |
58 | ||
59 | def probe_list(num_probes): | |
60 | l = [] | |
61 | for i in range(num_probes): | |
62 | d = {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data line %d' % i} | |
63 | l.append(d) | |
64 | return l | |
65 | ||
66 | class Decoder(srd.Decoder): | |
67 | api_version = 1 | |
68 | id = 'parallel' | |
69 | name = 'Parallel' | |
70 | longname = 'Parallel sync bus' | |
71 | desc = 'Generic parallel synchronous bus.' | |
72 | license = 'gplv2+' | |
73 | inputs = ['logic'] | |
74 | outputs = ['parallel'] | |
75 | probes = [ | |
76 | {'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'}, | |
77 | ] | |
78 | optional_probes = probe_list(8) | |
79 | options = { | |
80 | 'clock_edge': ['Clock edge to sample on', 'rising'], | |
81 | 'wordsize': ['Word size of the data', 1], | |
82 | 'endianness': ['Endianness of the data', 'little'], | |
83 | 'format': ['Data format', 'hex'], | |
84 | } | |
85 | annotations = [ | |
86 | ['items', 'Items'], | |
87 | ['words', 'Words'], | |
88 | ] | |
89 | ||
90 | def __init__(self): | |
91 | self.oldclk = None | |
92 | self.items = [] | |
93 | self.itemcount = 0 | |
94 | self.saved_item = None | |
95 | self.samplenum = 0 | |
96 | self.oldpins = None | |
97 | self.ss_item = self.es_item = None | |
98 | self.first = True | |
99 | self.state = 'IDLE' | |
100 | ||
101 | def start(self): | |
102 | self.out_proto = self.register(srd.OUTPUT_PYTHON) | |
103 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
104 | ||
105 | def putpb(self, data): | |
106 | self.put(self.ss_item, self.es_item, self.out_proto, data) | |
107 | ||
108 | def putb(self, data): | |
109 | self.put(self.ss_item, self.es_item, self.out_ann, data) | |
110 | ||
111 | def putpw(self, data): | |
112 | self.put(self.ss_word, self.es_word, self.out_proto, data) | |
113 | ||
114 | def putw(self, data): | |
115 | self.put(self.ss_word, self.es_word, self.out_ann, data) | |
116 | ||
117 | def handle_bits(self, datapins): | |
118 | # If this is the first item in a word, save its sample number. | |
119 | if self.itemcount == 0: | |
120 | self.ss_word = self.samplenum | |
121 | ||
122 | # Get the bits for this item. | |
123 | item, used_pins = 0, datapins.count(b'\x01') + datapins.count(b'\x00') | |
124 | for i in range(used_pins): | |
125 | item |= datapins[i] << i | |
126 | ||
127 | self.items.append(item) | |
128 | self.itemcount += 1 | |
129 | ||
130 | if self.first == True: | |
131 | # Save the start sample and item for later (no output yet). | |
132 | self.ss_item = self.samplenum | |
133 | self.first = False | |
134 | self.saved_item = item | |
135 | else: | |
136 | # Output the saved item (from the last CLK edge to the current). | |
137 | self.es_item = self.samplenum | |
138 | self.putpb(['ITEM', self.saved_item]) | |
139 | self.putb([0, ['%X' % self.saved_item]]) | |
140 | self.ss_item = self.samplenum | |
141 | self.saved_item = item | |
142 | ||
143 | endian, ws = self.options['endianness'], self.options['wordsize'] | |
144 | ||
145 | # Get as many items as the configured wordsize says. | |
146 | if self.itemcount < ws: | |
147 | return | |
148 | ||
149 | # Output annotations/proto for a word (a collection of items). | |
150 | word = 0 | |
151 | for i in range(ws): | |
152 | if endian == 'little': | |
153 | word |= self.items[i] << ((ws - 1 - i) * used_pins) | |
154 | elif endian == 'big': | |
155 | word |= self.items[i] << (i * used_pins) | |
156 | ||
157 | self.es_word = self.samplenum | |
158 | # self.putpw(['WORD', word]) | |
159 | # self.putw([1, ['%X' % word]]) | |
160 | self.ss_word = self.samplenum | |
161 | ||
162 | self.itemcount, self.items = 0, [] | |
163 | ||
164 | def find_clk_edge(self, clk, datapins): | |
165 | # Ignore sample if the clock pin hasn't changed. | |
166 | if clk == self.oldclk: | |
167 | return | |
168 | self.oldclk = clk | |
169 | ||
170 | # Sample data on rising/falling clock edge (depends on config). | |
171 | c = self.options['clock_edge'] | |
172 | if c == 'rising' and clk == 0: # Sample on rising clock edge. | |
173 | return | |
174 | elif c == 'falling' and clk == 1: # Sample on falling clock edge. | |
175 | return | |
176 | ||
177 | # Found the correct clock edge, now get the bits. | |
178 | self.handle_bits(datapins) | |
179 | ||
180 | def decode(self, ss, es, data): | |
181 | for (self.samplenum, pins) in data: | |
182 | ||
183 | # Ignore identical samples early on (for performance reasons). | |
184 | if self.oldpins == pins: | |
185 | continue | |
186 | self.oldpins = pins | |
187 | ||
188 | # State machine. | |
189 | if self.state == 'IDLE': | |
190 | self.find_clk_edge(pins[0], pins[1:]) | |
191 | else: | |
192 | raise Exception('Invalid state: %s' % self.state) | |
193 |