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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2017 Kevin Redon <kingkevin@cuvoodoo.info> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | ## | |
19 | ||
20 | import sigrokdecode as srd | |
21 | from collections import namedtuple | |
22 | ||
23 | ''' | |
24 | OUTPUT_PYTHON format: | |
25 | ||
26 | Packet: | |
27 | [namedtuple('ss': bit start sample number, | |
28 | 'es': bit end sample number, | |
29 | 'si': SI bit, | |
30 | 'so': SO bit, | |
31 | ), ...] | |
32 | ||
33 | Since address and word size are variable, a list of all bits in each packet | |
34 | need to be output. Since Microwire is a synchronous protocol with separate | |
35 | input and output lines (SI and SO) they are provided together, but because | |
36 | Microwire is half-duplex only the SI or SO bits will be considered at once. | |
37 | To be able to annotate correctly the instructions formed by the bit, the start | |
38 | and end sample number of each bit (pair of SI/SO bit) are provided. | |
39 | ''' | |
40 | ||
41 | PyPacket = namedtuple('PyPacket', 'ss es si so') | |
42 | Packet = namedtuple('Packet', 'samplenum matched cs sk si so') | |
43 | ||
44 | class Decoder(srd.Decoder): | |
45 | api_version = 3 | |
46 | id = 'microwire' | |
47 | name = 'Microwire' | |
48 | longname = 'Microwire' | |
49 | desc = '3-wire, half-duplex, synchronous serial bus.' | |
50 | license = 'gplv2+' | |
51 | inputs = ['logic'] | |
52 | outputs = ['microwire'] | |
53 | channels = ( | |
54 | {'id': 'cs', 'name': 'CS', 'desc': 'Chip select'}, | |
55 | {'id': 'sk', 'name': 'SK', 'desc': 'Clock'}, | |
56 | {'id': 'si', 'name': 'SI', 'desc': 'Slave in'}, | |
57 | {'id': 'so', 'name': 'SO', 'desc': 'Slave out'}, | |
58 | ) | |
59 | annotations = ( | |
60 | ('start-bit', 'Start bit'), | |
61 | ('si-bit', 'SI bit'), | |
62 | ('so-bit', 'SO bit'), | |
63 | ('status-check-ready', 'Status check ready'), | |
64 | ('status-check-busy', 'Status check busy'), | |
65 | ('warning', 'Warning'), | |
66 | ) | |
67 | annotation_rows = ( | |
68 | ('si-bits', 'SI bits', (0, 1)), | |
69 | ('so-bits', 'SO bits', (2,)), | |
70 | ('status', 'Status', (3, 4)), | |
71 | ('warnings', 'Warnings', (5,)), | |
72 | ) | |
73 | ||
74 | def start(self): | |
75 | self.out_python = self.register(srd.OUTPUT_PYTHON) | |
76 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
77 | ||
78 | def decode(self): | |
79 | while True: | |
80 | # Wait for slave to be selected on rising CS. | |
81 | cs, sk, si, so = self.wait({0: 'r'}) | |
82 | if sk: | |
83 | self.put(self.samplenum, self.samplenum, self.out_ann, | |
84 | [5, ['Clock should be low on start', | |
85 | 'Clock high on start', 'Clock high', 'SK high']]) | |
86 | sk = 0 # Enforce correct state for correct clock handling. | |
87 | # Because we don't know if this is bit communication or a | |
88 | # status check we have to collect the SI and SO values on SK | |
89 | # edges while the chip is selected and figure out afterwards. | |
90 | packet = [] | |
91 | while cs: | |
92 | # Save change. | |
93 | packet.append(Packet(self.samplenum, self.matched, cs, sk, si, so)) | |
94 | edge = 'r' if sk == 0 else 'f' | |
95 | cs, sk, si, so = self.wait([{0: 'l'}, {1: edge}, {3: 'e'}]) | |
96 | # Save last change. | |
97 | packet.append(Packet(self.samplenum, self.matched, cs, sk, si, so)) | |
98 | ||
99 | # Figure out if this is a status check. | |
100 | # Either there is no clock or no start bit (on first rising edge). | |
101 | status_check = True | |
102 | for change in packet: | |
103 | # Get first clock rising edge. | |
104 | if len(change.matched) > 1 and change.matched[1] and change.sk: | |
105 | if change.si: | |
106 | status_check = False | |
107 | break | |
108 | ||
109 | # The packet is for a status check. | |
110 | # SO low = busy, SO high = ready. | |
111 | # The SO signal might be noisy in the beginning because it starts | |
112 | # in high impedance. | |
113 | if status_check: | |
114 | start_samplenum = packet[0].samplenum | |
115 | bit_so = packet[0].so | |
116 | # Check for SO edges. | |
117 | for change in packet: | |
118 | if len(change.matched) > 2 and change.matched[2]: | |
119 | if bit_so == 0 and change.so: | |
120 | # Rising edge Busy -> Ready. | |
121 | self.put(start_samplenum, change.samplenum, | |
122 | self.out_ann, [4, ['Busy', 'B']]) | |
123 | start_samplenum = change.samplenum | |
124 | bit_so = change.so | |
125 | # Put last state. | |
126 | if bit_so == 0: | |
127 | self.put(start_samplenum, packet[-1].samplenum, | |
128 | self.out_ann, [4, ['Busy', 'B']]) | |
129 | else: | |
130 | self.put(start_samplenum, packet[-1].samplenum, | |
131 | self.out_ann, [3, ['Ready', 'R']]) | |
132 | else: | |
133 | # Bit communication. | |
134 | # Since the slave samples SI on clock rising edge we do the | |
135 | # same. Because the slave changes SO on clock rising edge we | |
136 | # sample on the falling edge. | |
137 | bit_start = 0 # Rising clock sample of bit start. | |
138 | bit_si = 0 # SI value at rising clock edge. | |
139 | bit_so = 0 # SO value at falling clock edge. | |
140 | start_bit = True # Start bit incoming (first bit). | |
141 | pydata = [] # Python output data. | |
142 | for change in packet: | |
143 | if len(change.matched) > 1 and change.matched[1]: | |
144 | # Clock edge. | |
145 | if change.sk: # Rising clock edge. | |
146 | if bit_start > 0: # Bit completed. | |
147 | if start_bit: | |
148 | if bit_si == 0: # Start bit missing. | |
149 | self.put(bit_start, change.samplenum, | |
150 | self.out_ann, | |
151 | [5, ['Start bit not high', | |
152 | 'Start bit low']]) | |
153 | else: | |
154 | self.put(bit_start, change.samplenum, | |
155 | self.out_ann, | |
156 | [0, ['Start bit', 'S']]) | |
157 | start_bit = False | |
158 | else: | |
159 | self.put(bit_start, change.samplenum, | |
160 | self.out_ann, | |
161 | [1, ['SI bit: %d' % bit_si, | |
162 | 'SI: %d' % bit_si, | |
163 | '%d' % bit_si]]) | |
164 | self.put(bit_start, change.samplenum, | |
165 | self.out_ann, | |
166 | [2, ['SO bit: %d' % bit_so, | |
167 | 'SO: %d' % bit_so, | |
168 | '%d' % bit_so]]) | |
169 | pydata.append(PyPacket(bit_start, | |
170 | change.samplenum, bit_si, bit_so)) | |
171 | bit_start = change.samplenum | |
172 | bit_si = change.si | |
173 | else: # Falling clock edge. | |
174 | bit_so = change.so | |
175 | elif change.matched[0] and \ | |
176 | change.cs == 0 and change.sk == 0: | |
177 | # End of packet. | |
178 | self.put(bit_start, change.samplenum, self.out_ann, | |
179 | [1, ['SI bit: %d' % bit_si, | |
180 | 'SI: %d' % bit_si, '%d' % bit_si]]) | |
181 | self.put(bit_start, change.samplenum, self.out_ann, | |
182 | [2, ['SO bit: %d' % bit_so, | |
183 | 'SO: %d' % bit_so, '%d' % bit_so]]) | |
184 | pydata.append(PyPacket(bit_start, change.samplenum, | |
185 | bit_si, bit_so)) | |
186 | self.put(packet[0].samplenum, packet[len(packet) - 1].samplenum, | |
187 | self.out_python, pydata) |