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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2014 Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | import sigrokdecode as srd | |
22 | ||
23 | # Helper dictionary for edge detection. | |
24 | edge_detector = { | |
25 | 'rising': lambda x, y: bool(not x and y), | |
26 | 'falling': lambda x, y: bool(x and not y), | |
27 | 'both': lambda x, y: bool(x ^ y), | |
28 | } | |
29 | ||
30 | class SamplerateError(Exception): | |
31 | pass | |
32 | ||
33 | class Decoder(srd.Decoder): | |
34 | api_version = 3 | |
35 | id = 'jitter' | |
36 | name = 'Jitter' | |
37 | longname = 'Timing jitter calculation' | |
38 | desc = 'Retrieves the timing jitter between two digital signals.' | |
39 | license = 'gplv2+' | |
40 | inputs = ['logic'] | |
41 | outputs = ['jitter'] | |
42 | channels = ( | |
43 | {'id': 'clk', 'name': 'Clock', 'desc': 'Clock reference channel'}, | |
44 | {'id': 'sig', 'name': 'Resulting signal', 'desc': 'Resulting signal controlled by the clock'}, | |
45 | ) | |
46 | options = ( | |
47 | {'id': 'clk_polarity', 'desc': 'Clock edge polarity', | |
48 | 'default': 'rising', 'values': ('rising', 'falling', 'both')}, | |
49 | {'id': 'sig_polarity', 'desc': 'Resulting signal edge polarity', | |
50 | 'default': 'rising', 'values': ('rising', 'falling', 'both')}, | |
51 | ) | |
52 | annotations = ( | |
53 | ('jitter', 'Jitter value'), | |
54 | ('clk_missed', 'Clock missed'), | |
55 | ('sig_missed', 'Signal missed'), | |
56 | ) | |
57 | annotation_rows = ( | |
58 | ('jitter', 'Jitter values', (0,)), | |
59 | ('clk_missed', 'Clock missed', (1,)), | |
60 | ('sig_missed', 'Signal missed', (2,)), | |
61 | ) | |
62 | binary = ( | |
63 | ('ascii-float', 'Jitter values as newline-separated ASCII floats'), | |
64 | ) | |
65 | ||
66 | def __init__(self): | |
67 | self.state = 'CLK' | |
68 | self.samplerate = None | |
69 | self.oldclk, self.oldsig = 0, 0 | |
70 | self.clk_start = None | |
71 | self.sig_start = None | |
72 | self.clk_missed = 0 | |
73 | self.sig_missed = 0 | |
74 | ||
75 | def start(self): | |
76 | self.clk_edge = edge_detector[self.options['clk_polarity']] | |
77 | self.sig_edge = edge_detector[self.options['sig_polarity']] | |
78 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
79 | self.out_binary = self.register(srd.OUTPUT_BINARY) | |
80 | self.out_clk_missed = self.register(srd.OUTPUT_META, | |
81 | meta=(int, 'Clock missed', 'Clock transition missed')) | |
82 | self.out_sig_missed = self.register(srd.OUTPUT_META, | |
83 | meta=(int, 'Signal missed', 'Resulting signal transition missed')) | |
84 | ||
85 | def metadata(self, key, value): | |
86 | if key == srd.SRD_CONF_SAMPLERATE: | |
87 | self.samplerate = value | |
88 | ||
89 | # Helper function for jitter time annotations. | |
90 | def putx(self, delta): | |
91 | # Adjust granularity. | |
92 | if delta == 0 or delta >= 1: | |
93 | delta_s = '%.1fs' % (delta) | |
94 | elif delta <= 1e-12: | |
95 | delta_s = '%.1ffs' % (delta * 1e15) | |
96 | elif delta <= 1e-9: | |
97 | delta_s = '%.1fps' % (delta * 1e12) | |
98 | elif delta <= 1e-6: | |
99 | delta_s = '%.1fns' % (delta * 1e9) | |
100 | elif delta <= 1e-3: | |
101 | delta_s = '%.1fμs' % (delta * 1e6) | |
102 | else: | |
103 | delta_s = '%.1fms' % (delta * 1e3) | |
104 | ||
105 | self.put(self.clk_start, self.sig_start, self.out_ann, [0, [delta_s]]) | |
106 | ||
107 | # Helper function for ASCII float jitter values (one value per line). | |
108 | def putb(self, delta): | |
109 | if delta is None: | |
110 | return | |
111 | # Format the delta to an ASCII float value terminated by a newline. | |
112 | x = str(delta) + '\n' | |
113 | self.put(self.clk_start, self.sig_start, self.out_binary, | |
114 | [0, x.encode('UTF-8')]) | |
115 | ||
116 | # Helper function for missed clock and signal annotations. | |
117 | def putm(self, data): | |
118 | self.put(self.samplenum, self.samplenum, self.out_ann, data) | |
119 | ||
120 | def handle_clk(self, clk, sig): | |
121 | if self.clk_start == self.samplenum: | |
122 | # Clock transition already treated. | |
123 | # We have done everything we can with this sample. | |
124 | return True | |
125 | ||
126 | if self.clk_edge(self.oldclk, clk): | |
127 | # Clock edge found. | |
128 | # We note the sample and move to the next state. | |
129 | self.clk_start = self.samplenum | |
130 | self.state = 'SIG' | |
131 | return False | |
132 | else: | |
133 | if self.sig_start is not None \ | |
134 | and self.sig_start != self.samplenum \ | |
135 | and self.sig_edge(self.oldsig, sig): | |
136 | # If any transition in the resulting signal | |
137 | # occurs while we are waiting for a clock, | |
138 | # we increase the missed signal counter. | |
139 | self.sig_missed += 1 | |
140 | self.put(self.samplenum, self.samplenum, self.out_sig_missed, self.sig_missed) | |
141 | self.putm([2, ['Missed signal', 'MS']]) | |
142 | # No clock edge found, we have done everything we | |
143 | # can with this sample. | |
144 | return True | |
145 | ||
146 | def handle_sig(self, clk, sig): | |
147 | if self.sig_start == self.samplenum: | |
148 | # Signal transition already treated. | |
149 | # We have done everything we can with this sample. | |
150 | return True | |
151 | ||
152 | if self.sig_edge(self.oldsig, sig): | |
153 | # Signal edge found. | |
154 | # We note the sample, calculate the jitter | |
155 | # and move to the next state. | |
156 | self.sig_start = self.samplenum | |
157 | self.state = 'CLK' | |
158 | # Calculate and report the timing jitter. | |
159 | delta = (self.sig_start - self.clk_start) / self.samplerate | |
160 | self.putx(delta) | |
161 | self.putb(delta) | |
162 | return False | |
163 | else: | |
164 | if self.clk_start != self.samplenum \ | |
165 | and self.clk_edge(self.oldclk, clk): | |
166 | # If any transition in the clock signal | |
167 | # occurs while we are waiting for a resulting | |
168 | # signal, we increase the missed clock counter. | |
169 | self.clk_missed += 1 | |
170 | self.put(self.samplenum, self.samplenum, self.out_clk_missed, self.clk_missed) | |
171 | self.putm([1, ['Missed clock', 'MC']]) | |
172 | # No resulting signal edge found, we have done | |
173 | # everything we can with this sample. | |
174 | return True | |
175 | ||
176 | def decode(self): | |
177 | if not self.samplerate: | |
178 | raise SamplerateError('Cannot decode without samplerate.') | |
179 | while True: | |
180 | # Wait for a transition on CLK and/or SIG. | |
181 | clk, sig = self.wait([{0: 'e'}, {1: 'e'}]) | |
182 | ||
183 | # State machine: | |
184 | # For each sample we can move 2 steps forward in the state machine. | |
185 | while True: | |
186 | # Clock state has the lead. | |
187 | if self.state == 'CLK': | |
188 | if self.handle_clk(clk, sig): | |
189 | break | |
190 | if self.state == 'SIG': | |
191 | if self.handle_sig(clk, sig): | |
192 | break | |
193 | ||
194 | # Save current CLK/SIG values for the next round. | |
195 | self.oldclk, self.oldsig = clk, sig |