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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2012-2020 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## Copyright (C) 2019 Zhiyuan Wan <dv.xw@qq.com> | |
6 | ## Copyright (C) 2019 Kongou Hikari <hikari@iloli.bid> | |
7 | ## | |
8 | ## This program is free software; you can redistribute it and/or modify | |
9 | ## it under the terms of the GNU General Public License as published by | |
10 | ## the Free Software Foundation; either version 2 of the License, or | |
11 | ## (at your option) any later version. | |
12 | ## | |
13 | ## This program is distributed in the hope that it will be useful, | |
14 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ## GNU General Public License for more details. | |
17 | ## | |
18 | ## You should have received a copy of the GNU General Public License | |
19 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. | |
20 | ## | |
21 | ||
22 | import sigrokdecode as srd | |
23 | from common.srdhelper import SrdStrEnum | |
24 | ||
25 | ''' | |
26 | OUTPUT_PYTHON format: | |
27 | ||
28 | Packet: | |
29 | [<ptype>, <pdata>] | |
30 | ||
31 | <ptype>: | |
32 | - 'NEW STATE': <pdata> is the new state of the JTAG state machine. | |
33 | Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN', | |
34 | 'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR', | |
35 | 'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR', | |
36 | 'EXIT2-IR', 'UPDATE-IR'. | |
37 | - 'IR TDI': Bitstring that was clocked into the IR register. | |
38 | - 'IR TDO': Bitstring that was clocked out of the IR register. | |
39 | - 'DR TDI': Bitstring that was clocked into the DR register. | |
40 | - 'DR TDO': Bitstring that was clocked out of the DR register. | |
41 | ||
42 | All bitstrings are a list consisting of two items. The first is a sequence | |
43 | of '1' and '0' characters (the right-most character is the LSB. Example: | |
44 | '01110001', where 1 is the LSB). The second item is a list of ss/es values | |
45 | for each bit that is in the bitstring. | |
46 | ''' | |
47 | ||
48 | s = 'TEST-LOGIC-RESET RUN-TEST/IDLE \ | |
49 | SELECT-DR-SCAN CAPTURE-DR UPDATE-DR PAUSE-DR SHIFT-DR EXIT1-DR EXIT2-DR \ | |
50 | SELECT-IR-SCAN CAPTURE-IR UPDATE-IR PAUSE-IR SHIFT-IR EXIT1-IR EXIT2-IR' | |
51 | St = SrdStrEnum.from_str('St', s) | |
52 | ||
53 | jtag_states = [s.value for s in St] | |
54 | ||
55 | s = 'EC SPARE TPDEL TPREV TPST RDYC DLYC SCNFMT CP OAC'.split() | |
56 | s = ['CJTAG_' + x for x in s] + ['OSCAN1', 'FOUR_WIRE'] | |
57 | CSt = SrdStrEnum.from_list('CSt', s) | |
58 | ||
59 | cjtag_states = [s.value for s in CSt] | |
60 | ||
61 | class Decoder(srd.Decoder): | |
62 | api_version = 3 | |
63 | id = 'cjtag' | |
64 | name = 'cJTAG' | |
65 | longname = 'Compact Joint Test Action Group (IEEE 1149.7)' | |
66 | desc = 'Protocol for testing, debugging, and flashing ICs.' | |
67 | license = 'gplv2+' | |
68 | inputs = ['logic'] | |
69 | outputs = ['jtag'] | |
70 | tags = ['Debug/trace'] | |
71 | channels = ( | |
72 | {'id': 'tckc', 'name': 'TCKC', 'desc': 'Test clock'}, | |
73 | {'id': 'tmsc', 'name': 'TMSC', 'desc': 'Test mode select'}, | |
74 | ) | |
75 | annotations = \ | |
76 | tuple([tuple([s.lower(), s]) for s in jtag_states]) + \ | |
77 | tuple([tuple([s.lower(), s]) for s in cjtag_states]) + ( \ | |
78 | ('bit-tdi', 'Bit (TDI)'), | |
79 | ('bit-tdo', 'Bit (TDO)'), | |
80 | ('bitstring-tdi', 'Bitstring (TDI)'), | |
81 | ('bitstring-tdo', 'Bitstring (TDO)'), | |
82 | ('bit-tms', 'Bit (TMS)'), | |
83 | ) | |
84 | annotation_rows = ( | |
85 | ('bits-tdi', 'Bits (TDI)', (28,)), | |
86 | ('bits-tdo', 'Bits (TDO)', (29,)), | |
87 | ('bitstrings-tdi', 'Bitstrings (TDI)', (30,)), | |
88 | ('bitstrings-tdo', 'Bitstrings (TDO)', (31,)), | |
89 | ('bits-tms', 'Bits (TMS)', (32,)), | |
90 | ('cjtag-states', 'CJTAG states', | |
91 | tuple(range(len(jtag_states), len(jtag_states + cjtag_states)))), | |
92 | ('jtag-states', 'JTAG states', tuple(range(len(jtag_states)))), | |
93 | ) | |
94 | ||
95 | def __init__(self): | |
96 | self.reset() | |
97 | ||
98 | def reset(self): | |
99 | # self.state = St.TEST_LOGIC_RESET | |
100 | self.state = St.RUN_TEST_IDLE | |
101 | self.cjtagstate = CSt.FOUR_WIRE | |
102 | self.oldcjtagstate = None | |
103 | self.escape_edges = 0 | |
104 | self.oaclen = 0 | |
105 | self.oldtms = 0 | |
106 | self.oacp = 0 | |
107 | self.oscan1cycle = 0 | |
108 | self.oldstate = None | |
109 | self.bits_tdi = [] | |
110 | self.bits_tdo = [] | |
111 | self.bits_samplenums_tdi = [] | |
112 | self.bits_samplenums_tdo = [] | |
113 | self.ss_item = self.es_item = None | |
114 | self.ss_bitstring = self.es_bitstring = None | |
115 | self.saved_item = None | |
116 | self.first = True | |
117 | self.first_bit = True | |
118 | ||
119 | def start(self): | |
120 | self.out_python = self.register(srd.OUTPUT_PYTHON) | |
121 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
122 | ||
123 | def putx(self, data): | |
124 | self.put(self.ss_item, self.es_item, self.out_ann, data) | |
125 | ||
126 | def putp(self, data): | |
127 | self.put(self.ss_item, self.es_item, self.out_python, data) | |
128 | ||
129 | def putx_bs(self, data): | |
130 | self.put(self.ss_bitstring, self.es_bitstring, self.out_ann, data) | |
131 | ||
132 | def putp_bs(self, data): | |
133 | self.put(self.ss_bitstring, self.es_bitstring, self.out_python, data) | |
134 | ||
135 | def advance_state_machine(self, tms): | |
136 | self.oldstate = self.state | |
137 | ||
138 | if self.cjtagstate.value.startswith('CJTAG_'): | |
139 | self.oacp += 1 | |
140 | if self.oacp > 4 and self.oaclen == 12: | |
141 | self.cjtagstate = CSt.CJTAG_EC | |
142 | ||
143 | if self.oacp == 8 and tms == 0: | |
144 | self.oaclen = 36 | |
145 | if self.oacp > 8 and self.oaclen == 36: | |
146 | self.cjtagstate = CSt.CJTAG_SPARE | |
147 | if self.oacp > 13 and self.oaclen == 36: | |
148 | self.cjtagstate = CSt.CJTAG_TPDEL | |
149 | if self.oacp > 16 and self.oaclen == 36: | |
150 | self.cjtagstate = CSt.CJTAG_TPREV | |
151 | if self.oacp > 18 and self.oaclen == 36: | |
152 | self.cjtagstate = CSt.CJTAG_TPST | |
153 | if self.oacp > 23 and self.oaclen == 36: | |
154 | self.cjtagstate = CSt.CJTAG_RDYC | |
155 | if self.oacp > 25 and self.oaclen == 36: | |
156 | self.cjtagstate = CSt.CJTAG_DLYC | |
157 | if self.oacp > 27 and self.oaclen == 36: | |
158 | self.cjtagstate = CSt.CJTAG_SCNFMT | |
159 | ||
160 | if self.oacp > 8 and self.oaclen == 12: | |
161 | self.cjtagstate = CSt.CJTAG_CP | |
162 | if self.oacp > 32 and self.oaclen == 36: | |
163 | self.cjtagstate = CSt.CJTAG_CP | |
164 | ||
165 | if self.oacp > self.oaclen: | |
166 | self.cjtagstate = CSt.OSCAN1 | |
167 | self.oscan1cycle = 1 | |
168 | # Because Nuclei cJTAG device asserts a reset during cJTAG | |
169 | # online activating. | |
170 | self.state = St.TEST_LOGIC_RESET | |
171 | return | |
172 | ||
173 | # Intro "tree" | |
174 | if self.state == St.TEST_LOGIC_RESET: | |
175 | self.state = St.TEST_LOGIC_RESET if (tms) else St.RUN_TEST_IDLE | |
176 | elif self.state == St.RUN_TEST_IDLE: | |
177 | self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE | |
178 | ||
179 | # DR "tree" | |
180 | elif self.state == St.SELECT_DR_SCAN: | |
181 | self.state = St.SELECT_IR_SCAN if (tms) else St.CAPTURE_DR | |
182 | elif self.state == St.CAPTURE_DR: | |
183 | self.state = St.EXIT1_DR if (tms) else St.SHIFT_DR | |
184 | elif self.state == St.SHIFT_DR: | |
185 | self.state = St.EXIT1_DR if (tms) else St.SHIFT_DR | |
186 | elif self.state == St.EXIT1_DR: | |
187 | self.state = St.UPDATE_DR if (tms) else St.PAUSE_DR | |
188 | elif self.state == St.PAUSE_DR: | |
189 | self.state = St.EXIT2_DR if (tms) else St.PAUSE_DR | |
190 | elif self.state == St.EXIT2_DR: | |
191 | self.state = St.UPDATE_DR if (tms) else St.SHIFT_DR | |
192 | elif self.state == St.UPDATE_DR: | |
193 | self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE | |
194 | ||
195 | # IR "tree" | |
196 | elif self.state == St.SELECT_IR_SCAN: | |
197 | self.state = St.TEST_LOGIC_RESET if (tms) else St.CAPTURE_IR | |
198 | elif self.state == St.CAPTURE_IR: | |
199 | self.state = St.EXIT1_IR if (tms) else St.SHIFT_IR | |
200 | elif self.state == St.SHIFT_IR: | |
201 | self.state = St.EXIT1_IR if (tms) else St.SHIFT_IR | |
202 | elif self.state == St.EXIT1_IR: | |
203 | self.state = St.UPDATE_IR if (tms) else St.PAUSE_IR | |
204 | elif self.state == St.PAUSE_IR: | |
205 | self.state = St.EXIT2_IR if (tms) else St.PAUSE_IR | |
206 | elif self.state == St.EXIT2_IR: | |
207 | self.state = St.UPDATE_IR if (tms) else St.SHIFT_IR | |
208 | elif self.state == St.UPDATE_IR: | |
209 | self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE | |
210 | ||
211 | def handle_rising_tckc_edge(self, tdi, tdo, tck, tms): | |
212 | ||
213 | # Rising TCK edges always advance the state machine. | |
214 | self.advance_state_machine(tms) | |
215 | ||
216 | if self.first: | |
217 | # Save the start sample and item for later (no output yet). | |
218 | self.ss_item = self.samplenum | |
219 | self.first = False | |
220 | else: | |
221 | # Output the saved item (from the last CLK edge to the current). | |
222 | self.es_item = self.samplenum | |
223 | # Output the old state (from last rising TCK edge to current one). | |
224 | self.putx([jtag_states.index(self.oldstate.value), [self.oldstate.value]]) | |
225 | self.putp(['NEW STATE', self.state.value]) | |
226 | ||
227 | self.putx([len(jtag_states) + cjtag_states.index(self.oldcjtagstate.value), | |
228 | [self.oldcjtagstate.value]]) | |
229 | if (self.oldcjtagstate.value.startswith('CJTAG_')): | |
230 | self.putx([32, [str(self.oldtms)]]) | |
231 | self.oldtms = tms | |
232 | ||
233 | # Upon SHIFT-*/EXIT1-* collect the current TDI/TDO values. | |
234 | if self.oldstate.value.startswith('SHIFT-') or \ | |
235 | self.oldstate.value.startswith('EXIT1-'): | |
236 | if self.first_bit: | |
237 | self.ss_bitstring = self.samplenum | |
238 | self.first_bit = False | |
239 | else: | |
240 | self.putx([28, [str(self.bits_tdi[0])]]) | |
241 | self.putx([29, [str(self.bits_tdo[0])]]) | |
242 | # Use self.samplenum as ES of the previous bit. | |
243 | self.bits_samplenums_tdi[0][1] = self.samplenum | |
244 | self.bits_samplenums_tdo[0][1] = self.samplenum | |
245 | ||
246 | self.bits_tdi.insert(0, tdi) | |
247 | self.bits_tdo.insert(0, tdo) | |
248 | ||
249 | # Use self.samplenum as SS of the current bit. | |
250 | self.bits_samplenums_tdi.insert(0, [self.samplenum, -1]) | |
251 | self.bits_samplenums_tdo.insert(0, [self.samplenum, -1]) | |
252 | ||
253 | # Output all TDI/TDO bits if we just switched to UPDATE-*. | |
254 | if self.state.value.startswith('UPDATE-'): | |
255 | ||
256 | self.es_bitstring = self.samplenum | |
257 | ||
258 | t = self.state.value[-2:] + ' TDI' | |
259 | b = ''.join(map(str, self.bits_tdi[1:])) | |
260 | h = ' (0x%x' % int('0b0' + b, 2) + ')' | |
261 | s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi[1:])) + ' bits' | |
262 | self.putx_bs([30, [s]]) | |
263 | self.putp_bs([t, [b, self.bits_samplenums_tdi[1:]]]) | |
264 | self.bits_tdi = [] | |
265 | self.bits_samplenums_tdi = [] | |
266 | ||
267 | t = self.state.value[-2:] + ' TDO' | |
268 | b = ''.join(map(str, self.bits_tdo[1:])) | |
269 | h = ' (0x%x' % int('0b0' + b, 2) + ')' | |
270 | s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo[1:])) + ' bits' | |
271 | self.putx_bs([31, [s]]) | |
272 | self.putp_bs([t, [b, self.bits_samplenums_tdo[1:]]]) | |
273 | self.bits_tdo = [] | |
274 | self.bits_samplenums_tdo = [] | |
275 | ||
276 | self.first_bit = True | |
277 | ||
278 | self.ss_bitstring = self.samplenum | |
279 | ||
280 | self.ss_item = self.samplenum | |
281 | ||
282 | def handle_tmsc_edge(self): | |
283 | self.escape_edges += 1 | |
284 | ||
285 | def handle_tapc_state(self): | |
286 | self.oldcjtagstate = self.cjtagstate | |
287 | ||
288 | if self.escape_edges >= 8: | |
289 | self.cjtagstate = CSt.FOUR_WIRE | |
290 | if self.escape_edges == 6: | |
291 | self.cjtagstate = CSt.CJTAG_OAC | |
292 | self.oacp = 0 | |
293 | self.oaclen = 12 | |
294 | ||
295 | self.escape_edges = 0 | |
296 | ||
297 | def decode(self): | |
298 | tdi = tms = tdo = 0 | |
299 | ||
300 | while True: | |
301 | # Wait for a rising edge on TCKC. | |
302 | tckc, tmsc = self.wait({0: 'r'}) | |
303 | self.handle_tapc_state() | |
304 | ||
305 | if self.cjtagstate == CSt.OSCAN1: | |
306 | if self.oscan1cycle == 0: # nTDI | |
307 | tdi = 1 if (tmsc == 0) else 0 | |
308 | self.oscan1cycle = 1 | |
309 | elif self.oscan1cycle == 1: # TMS | |
310 | tms = tmsc | |
311 | self.oscan1cycle = 2 | |
312 | elif self.oscan1cycle == 2: # TDO | |
313 | tdo = tmsc | |
314 | self.handle_rising_tckc_edge(tdi, tdo, tckc, tms) | |
315 | self.oscan1cycle = 0 | |
316 | else: | |
317 | self.handle_rising_tckc_edge(None, None, tckc, tmsc) | |
318 | ||
319 | while (tckc == 1): | |
320 | tckc, tmsc_n = self.wait([{0: 'f'}, {1: 'e'}]) | |
321 | if tmsc_n != tmsc: | |
322 | tmsc = tmsc_n | |
323 | self.handle_tmsc_edge() |