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f4816ac6 ML |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2012 Martin Ling <martin-git@earth.li> | |
88e429c9 | 5 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> |
bafd4890 | 6 | * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de> |
f4816ac6 ML |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
6ec6c43b | 22 | #include <config.h> |
f4816ac6 | 23 | #include <stdlib.h> |
e0b7d23c ML |
24 | #include <stdarg.h> |
25 | #include <unistd.h> | |
26 | #include <errno.h> | |
a3df166f | 27 | #include <string.h> |
254dd102 | 28 | #include <math.h> |
bafd4890 ML |
29 | #include <ctype.h> |
30 | #include <time.h> | |
f4816ac6 | 31 | #include <glib.h> |
c1aae900 | 32 | #include <libsigrok/libsigrok.h> |
f4816ac6 | 33 | #include "libsigrok-internal.h" |
5a1afc09 | 34 | #include "scpi.h" |
f4816ac6 ML |
35 | #include "protocol.h" |
36 | ||
bafd4890 ML |
37 | /* |
38 | * This is a unified protocol driver for the DS1000 and DS2000 series. | |
39 | * | |
40 | * DS1000 support tested with a Rigol DS1102D. | |
41 | * | |
42 | * DS2000 support tested with a Rigol DS2072 using firmware version 01.01.00.02. | |
43 | * | |
44 | * The Rigol DS2000 series scopes try to adhere to the IEEE 488.2 (I think) | |
45 | * standard. If you want to read it - it costs real money... | |
46 | * | |
47 | * Every response from the scope has a linefeed appended because the | |
48 | * standard says so. In principle this could be ignored because sending the | |
49 | * next command clears the output queue of the scope. This driver tries to | |
50 | * avoid doing that because it may cause an error being generated inside the | |
51 | * scope and who knows what bugs the firmware has WRT this. | |
52 | * | |
53 | * Waveform data is transferred in a format called "arbitrary block program | |
54 | * data" specified in IEEE 488.2. See Agilents programming manuals for their | |
55 | * 2000/3000 series scopes for a nice description. | |
56 | * | |
57 | * Each data block from the scope has a header, e.g. "#900000001400". | |
58 | * The '#' marks the start of a block. | |
59 | * Next is one ASCII decimal digit between 1 and 9, this gives the number of | |
60 | * ASCII decimal digits following. | |
61 | * Last are the ASCII decimal digits giving the number of bytes (not | |
62 | * samples!) in the block. | |
63 | * | |
64 | * After this header as many data bytes as indicated follow. | |
65 | * | |
66 | * Each data block has a trailing linefeed too. | |
67 | */ | |
68 | ||
bafd4890 ML |
69 | static int parse_int(const char *str, int *ret) |
70 | { | |
71 | char *e; | |
72 | long tmp; | |
73 | ||
74 | errno = 0; | |
75 | tmp = strtol(str, &e, 10); | |
76 | if (e == str || *e != '\0') { | |
77 | sr_dbg("Failed to parse integer: '%s'", str); | |
78 | return SR_ERR; | |
79 | } | |
80 | if (errno) { | |
81 | sr_dbg("Failed to parse integer: '%s', numerical overflow", str); | |
82 | return SR_ERR; | |
83 | } | |
84 | if (tmp > INT_MAX || tmp < INT_MIN) { | |
85 | sr_dbg("Failed to parse integer: '%s', value to large/small", str); | |
86 | return SR_ERR; | |
87 | } | |
88 | ||
89 | *ret = (int)tmp; | |
90 | return SR_OK; | |
91 | } | |
92 | ||
babab622 ML |
93 | /* Set the next event to wait for in rigol_ds_receive */ |
94 | static void rigol_ds_set_wait_event(struct dev_context *devc, enum wait_events event) | |
95 | { | |
96 | if (event == WAIT_STOP) | |
97 | devc->wait_status = 2; | |
98 | else | |
99 | devc->wait_status = 1; | |
100 | devc->wait_event = event; | |
101 | } | |
102 | ||
bafd4890 | 103 | /* |
babab622 ML |
104 | * Waiting for a event will return a timeout after 2 to 3 seconds in order |
105 | * to not block the application. | |
bafd4890 | 106 | */ |
babab622 | 107 | static int rigol_ds_event_wait(const struct sr_dev_inst *sdi, char status1, char status2) |
bafd4890 | 108 | { |
334fbc2a | 109 | char *buf; |
bafd4890 ML |
110 | struct dev_context *devc; |
111 | time_t start; | |
112 | ||
113 | if (!(devc = sdi->priv)) | |
114 | return SR_ERR; | |
115 | ||
116 | start = time(NULL); | |
117 | ||
118 | /* | |
119 | * Trigger status may return: | |
babab622 ML |
120 | * "TD" or "T'D" - triggered |
121 | * "AUTO" - autotriggered | |
122 | * "RUN" - running | |
123 | * "WAIT" - waiting for trigger | |
124 | * "STOP" - stopped | |
bafd4890 ML |
125 | */ |
126 | ||
babab622 | 127 | if (devc->wait_status == 1) { |
bafd4890 ML |
128 | do { |
129 | if (time(NULL) - start >= 3) { | |
130 | sr_dbg("Timeout waiting for trigger"); | |
131 | return SR_ERR_TIMEOUT; | |
132 | } | |
133 | ||
334fbc2a | 134 | if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK) |
bafd4890 | 135 | return SR_ERR; |
babab622 | 136 | } while (buf[0] == status1 || buf[0] == status2); |
bafd4890 | 137 | |
babab622 | 138 | devc->wait_status = 2; |
bafd4890 | 139 | } |
babab622 | 140 | if (devc->wait_status == 2) { |
bafd4890 ML |
141 | do { |
142 | if (time(NULL) - start >= 3) { | |
143 | sr_dbg("Timeout waiting for trigger"); | |
144 | return SR_ERR_TIMEOUT; | |
145 | } | |
146 | ||
334fbc2a | 147 | if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK) |
bafd4890 | 148 | return SR_ERR; |
babab622 | 149 | } while (buf[0] != status1 && buf[0] != status2); |
bafd4890 | 150 | |
babab622 | 151 | rigol_ds_set_wait_event(devc, WAIT_NONE); |
bafd4890 ML |
152 | } |
153 | ||
154 | return SR_OK; | |
155 | } | |
156 | ||
157 | /* | |
babab622 ML |
158 | * For live capture we need to wait for a new trigger event to ensure that |
159 | * sample data is not returned twice. | |
bafd4890 ML |
160 | * |
161 | * Unfortunately this will never really work because for sufficiently fast | |
babab622 | 162 | * timebases and trigger rates it just can't catch the status changes. |
bafd4890 ML |
163 | * |
164 | * What would be needed is a trigger event register with autoreset like the | |
165 | * Agilents have. The Rigols don't seem to have anything like this. | |
166 | * | |
167 | * The workaround is to only wait for the trigger when the timebase is slow | |
168 | * enough. Of course this means that for faster timebases sample data can be | |
babab622 ML |
169 | * returned multiple times, this effect is mitigated somewhat by sleeping |
170 | * for about one sweep time in that case. | |
bafd4890 | 171 | */ |
babab622 | 172 | static int rigol_ds_trigger_wait(const struct sr_dev_inst *sdi) |
bafd4890 ML |
173 | { |
174 | struct dev_context *devc; | |
babab622 | 175 | long s; |
bafd4890 ML |
176 | |
177 | if (!(devc = sdi->priv)) | |
178 | return SR_ERR; | |
179 | ||
176d785d | 180 | /* |
babab622 ML |
181 | * If timebase < 50 msecs/DIV just sleep about one sweep time except |
182 | * for really fast sweeps. | |
183 | */ | |
c2b394d5 | 184 | if (devc->timebase < 0.0499) { |
babab622 ML |
185 | if (devc->timebase > 0.99e-6) { |
186 | /* | |
187 | * Timebase * num hor. divs * 85(%) * 1e6(usecs) / 100 | |
188 | * -> 85 percent of sweep time | |
189 | */ | |
569d4dbd | 190 | s = (devc->timebase * devc->model->series->num_horizontal_divs |
babab622 ML |
191 | * 85e6) / 100L; |
192 | sr_spew("Sleeping for %ld usecs instead of trigger-wait", s); | |
193 | g_usleep(s); | |
194 | } | |
195 | rigol_ds_set_wait_event(devc, WAIT_NONE); | |
196 | return SR_OK; | |
197 | } else { | |
198 | return rigol_ds_event_wait(sdi, 'T', 'A'); | |
199 | } | |
200 | } | |
bafd4890 | 201 | |
babab622 ML |
202 | /* Wait for scope to got to "Stop" in single shot mode */ |
203 | static int rigol_ds_stop_wait(const struct sr_dev_inst *sdi) | |
204 | { | |
205 | return rigol_ds_event_wait(sdi, 'S', 'S'); | |
206 | } | |
207 | ||
208 | /* Check that a single shot acquisition actually succeeded on the DS2000 */ | |
209 | static int rigol_ds_check_stop(const struct sr_dev_inst *sdi) | |
210 | { | |
211 | struct dev_context *devc; | |
ba7dd8bb | 212 | struct sr_channel *ch; |
babab622 ML |
213 | int tmp; |
214 | ||
215 | if (!(devc = sdi->priv)) | |
bafd4890 | 216 | return SR_ERR; |
babab622 | 217 | |
ba7dd8bb | 218 | ch = devc->channel_entry->data; |
821fbcad | 219 | |
702f42e8 | 220 | if (devc->model->series->protocol != PROTOCOL_V3) |
e086b750 ML |
221 | return SR_OK; |
222 | ||
01dd7a4c | 223 | if (ch->type == SR_CHANNEL_LOGIC) { |
8cd15dd4 | 224 | if (rigol_ds_config_set(sdi, ":WAV:SOUR LA") != SR_OK) |
01dd7a4c ML |
225 | return SR_ERR; |
226 | } else { | |
227 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", | |
228 | ch->index + 1) != SR_OK) | |
229 | return SR_ERR; | |
230 | } | |
babab622 | 231 | /* Check that the number of samples will be accepted */ |
01dd7a4c ML |
232 | if (rigol_ds_config_set(sdi, ":WAV:POIN %d", |
233 | ch->type == SR_CHANNEL_LOGIC ? | |
234 | devc->digital_frame_size : | |
235 | devc->analog_frame_size) != SR_OK) | |
babab622 | 236 | return SR_ERR; |
334fbc2a | 237 | if (sr_scpi_get_int(sdi->conn, "*ESR?", &tmp) != SR_OK) |
bafd4890 | 238 | return SR_ERR; |
babab622 ML |
239 | /* |
240 | * If we get an "Execution error" the scope went from "Single" to | |
241 | * "Stop" without actually triggering. There is no waveform | |
242 | * displayed and trying to download one will fail - the scope thinks | |
243 | * it has 1400 samples (like display memory) and the driver thinks | |
244 | * it has a different number of samples. | |
245 | * | |
246 | * In that case just try to capture something again. Might still | |
247 | * fail in interesting ways. | |
248 | * | |
249 | * Ain't firmware fun? | |
250 | */ | |
251 | if (tmp & 0x10) { | |
252 | sr_warn("Single shot acquisition failed, retrying..."); | |
253 | /* Sleep a bit, otherwise the single shot will often fail */ | |
1a46cc62 | 254 | g_usleep(500 * 1000); |
38354d9d | 255 | rigol_ds_config_set(sdi, ":SING"); |
babab622 | 256 | rigol_ds_set_wait_event(devc, WAIT_STOP); |
bafd4890 | 257 | return SR_ERR; |
babab622 | 258 | } |
bafd4890 | 259 | |
babab622 ML |
260 | return SR_OK; |
261 | } | |
bafd4890 | 262 | |
babab622 ML |
263 | /* Wait for enough data becoming available in scope output buffer */ |
264 | static int rigol_ds_block_wait(const struct sr_dev_inst *sdi) | |
265 | { | |
334fbc2a | 266 | char *buf; |
babab622 ML |
267 | struct dev_context *devc; |
268 | time_t start; | |
269 | int len; | |
270 | ||
271 | if (!(devc = sdi->priv)) | |
272 | return SR_ERR; | |
273 | ||
702f42e8 | 274 | if (devc->model->series->protocol == PROTOCOL_V3) { |
babab622 | 275 | |
4472867a ML |
276 | start = time(NULL); |
277 | ||
278 | do { | |
279 | if (time(NULL) - start >= 3) { | |
280 | sr_dbg("Timeout waiting for data block"); | |
281 | return SR_ERR_TIMEOUT; | |
282 | } | |
babab622 | 283 | |
4472867a ML |
284 | /* |
285 | * The scope copies data really slowly from sample | |
286 | * memory to its output buffer, so try not to bother | |
287 | * it too much with SCPI requests but don't wait too | |
288 | * long for short sample frame sizes. | |
289 | */ | |
1a46cc62 | 290 | g_usleep(devc->analog_frame_size < (15 * 1000) ? (100 * 1000) : (1000 * 1000)); |
4472867a ML |
291 | |
292 | /* "READ,nnnn" (still working) or "IDLE,nnnn" (finished) */ | |
293 | if (sr_scpi_get_string(sdi->conn, ":WAV:STAT?", &buf) != SR_OK) | |
294 | return SR_ERR; | |
295 | ||
296 | if (parse_int(buf + 5, &len) != SR_OK) | |
297 | return SR_ERR; | |
1a46cc62 | 298 | } while (buf[0] == 'R' && len < (1000 * 1000)); |
4472867a | 299 | } |
babab622 ML |
300 | |
301 | rigol_ds_set_wait_event(devc, WAIT_NONE); | |
302 | ||
303 | return SR_OK; | |
304 | } | |
305 | ||
38354d9d ML |
306 | /* Send a configuration setting. */ |
307 | SR_PRIV int rigol_ds_config_set(const struct sr_dev_inst *sdi, const char *format, ...) | |
308 | { | |
309 | struct dev_context *devc = sdi->priv; | |
310 | va_list args; | |
311 | int ret; | |
312 | ||
313 | va_start(args, format); | |
314 | ret = sr_scpi_send_variadic(sdi->conn, format, args); | |
315 | va_end(args); | |
316 | ||
317 | if (ret != SR_OK) | |
318 | return SR_ERR; | |
319 | ||
569d4dbd | 320 | if (devc->model->series->protocol == PROTOCOL_V2) { |
38354d9d ML |
321 | /* The DS1000 series needs this stupid delay, *OPC? doesn't work. */ |
322 | sr_spew("delay %dms", 100); | |
1a46cc62 | 323 | g_usleep(100 * 1000); |
38354d9d ML |
324 | return SR_OK; |
325 | } else { | |
326 | return sr_scpi_get_opc(sdi->conn); | |
327 | } | |
328 | } | |
329 | ||
babab622 ML |
330 | /* Start capturing a new frameset */ |
331 | SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi) | |
332 | { | |
333 | struct dev_context *devc; | |
e086b750 | 334 | gchar *trig_mode; |
702f42e8 | 335 | unsigned int num_channels, i, j; |
e4204b17 | 336 | int buffer_samples; |
babab622 ML |
337 | |
338 | if (!(devc = sdi->priv)) | |
339 | return SR_ERR; | |
340 | ||
8cd15dd4 UH |
341 | if (devc->limit_frames == 0) |
342 | sr_dbg("Starting data capture for frameset %" PRIu64, | |
343 | devc->num_frames + 1); | |
344 | else | |
345 | sr_dbg("Starting data capture for frameset %" PRIu64 " of %" | |
346 | PRIu64, devc->num_frames + 1, devc->limit_frames); | |
babab622 | 347 | |
569d4dbd ML |
348 | switch (devc->model->series->protocol) { |
349 | case PROTOCOL_V1: | |
350 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); | |
351 | break; | |
352 | case PROTOCOL_V2: | |
353 | if (devc->data_source == DATA_SOURCE_LIVE) { | |
354 | if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE NORMAL") != SR_OK) | |
e086b750 | 355 | return SR_ERR; |
569d4dbd | 356 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); |
e086b750 | 357 | } else { |
e086b750 ML |
358 | if (rigol_ds_config_set(sdi, ":STOP") != SR_OK) |
359 | return SR_ERR; | |
360 | if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE RAW") != SR_OK) | |
361 | return SR_ERR; | |
362 | if (sr_scpi_get_string(sdi->conn, ":TRIG:MODE?", &trig_mode) != SR_OK) | |
363 | return SR_ERR; | |
364 | if (rigol_ds_config_set(sdi, ":TRIG:%s:SWE SING", trig_mode) != SR_OK) | |
365 | return SR_ERR; | |
366 | if (rigol_ds_config_set(sdi, ":RUN") != SR_OK) | |
367 | return SR_ERR; | |
569d4dbd ML |
368 | rigol_ds_set_wait_event(devc, WAIT_STOP); |
369 | } | |
370 | break; | |
371 | case PROTOCOL_V3: | |
702f42e8 | 372 | case PROTOCOL_V4: |
e4204b17 | 373 | case PROTOCOL_V5: |
569d4dbd ML |
374 | if (rigol_ds_config_set(sdi, ":WAV:FORM BYTE") != SR_OK) |
375 | return SR_ERR; | |
376 | if (devc->data_source == DATA_SOURCE_LIVE) { | |
377 | if (rigol_ds_config_set(sdi, ":WAV:MODE NORM") != SR_OK) | |
378 | return SR_ERR; | |
702f42e8 ML |
379 | devc->analog_frame_size = devc->model->series->live_samples; |
380 | devc->digital_frame_size = devc->model->series->live_samples; | |
569d4dbd | 381 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); |
e086b750 | 382 | } else { |
702f42e8 ML |
383 | if (devc->model->series->protocol == PROTOCOL_V3) { |
384 | if (rigol_ds_config_set(sdi, ":WAV:MODE RAW") != SR_OK) | |
385 | return SR_ERR; | |
e4204b17 | 386 | } else if (devc->model->series->protocol >= PROTOCOL_V4) { |
702f42e8 ML |
387 | num_channels = 0; |
388 | ||
389 | /* Channels 3 and 4 are multiplexed with D0-7 and D8-15 */ | |
390 | for (i = 0; i < devc->model->analog_channels; i++) { | |
391 | if (devc->analog_channels[i]) { | |
392 | num_channels++; | |
393 | } else if (i >= 2 && devc->model->has_digital) { | |
394 | for (j = 0; j < 8; j++) { | |
395 | if (devc->digital_channels[8 * (i - 2) + j]) { | |
396 | num_channels++; | |
397 | break; | |
398 | } | |
399 | } | |
400 | } | |
401 | } | |
402 | ||
e4204b17 UH |
403 | buffer_samples = devc->model->series->buffer_samples; |
404 | if (buffer_samples == 0) | |
405 | { | |
406 | /* The DS4000 series does not have a fixed memory depth, it | |
407 | * can be chosen from the menu and also varies with number | |
408 | * of active channels. Retrieve the actual number with the | |
409 | * ACQ:MDEP command. */ | |
410 | sr_scpi_get_int(sdi->conn, "ACQ:MDEP?", &buffer_samples); | |
411 | devc->analog_frame_size = devc->digital_frame_size = | |
412 | buffer_samples; | |
413 | } | |
414 | else | |
415 | { | |
416 | /* The DS1000Z series has a fixed memory depth which we | |
417 | * need to divide correctly according to the number of | |
418 | * active channels. */ | |
419 | devc->analog_frame_size = devc->digital_frame_size = | |
420 | num_channels == 1 ? | |
421 | buffer_samples : | |
422 | num_channels == 2 ? | |
423 | buffer_samples / 2 : | |
424 | buffer_samples / 4; | |
425 | } | |
702f42e8 ML |
426 | } |
427 | ||
e086b750 ML |
428 | if (rigol_ds_config_set(sdi, ":SING") != SR_OK) |
429 | return SR_ERR; | |
569d4dbd | 430 | rigol_ds_set_wait_event(devc, WAIT_STOP); |
e086b750 | 431 | } |
569d4dbd | 432 | break; |
bafd4890 ML |
433 | } |
434 | ||
435 | return SR_OK; | |
436 | } | |
437 | ||
babab622 ML |
438 | /* Start reading data from the current channel */ |
439 | SR_PRIV int rigol_ds_channel_start(const struct sr_dev_inst *sdi) | |
440 | { | |
441 | struct dev_context *devc; | |
ba7dd8bb | 442 | struct sr_channel *ch; |
babab622 ML |
443 | |
444 | if (!(devc = sdi->priv)) | |
445 | return SR_ERR; | |
446 | ||
ba7dd8bb | 447 | ch = devc->channel_entry->data; |
821fbcad | 448 | |
ba7dd8bb | 449 | sr_dbg("Starting reading data from channel %d", ch->index + 1); |
babab622 | 450 | |
2ea67fc9 | 451 | switch (devc->model->series->protocol) { |
702f42e8 ML |
452 | case PROTOCOL_V1: |
453 | case PROTOCOL_V2: | |
3f239f08 | 454 | if (ch->type == SR_CHANNEL_LOGIC) { |
677f85d0 ML |
455 | if (sr_scpi_send(sdi->conn, ":WAV:DATA? DIG") != SR_OK) |
456 | return SR_ERR; | |
457 | } else { | |
821fbcad | 458 | if (sr_scpi_send(sdi->conn, ":WAV:DATA? CHAN%d", |
ba7dd8bb | 459 | ch->index + 1) != SR_OK) |
677f85d0 ML |
460 | return SR_ERR; |
461 | } | |
e086b750 | 462 | rigol_ds_set_wait_event(devc, WAIT_NONE); |
702f42e8 ML |
463 | break; |
464 | case PROTOCOL_V3: | |
01dd7a4c | 465 | if (ch->type == SR_CHANNEL_LOGIC) { |
8cd15dd4 | 466 | if (rigol_ds_config_set(sdi, ":WAV:SOUR LA") != SR_OK) |
01dd7a4c ML |
467 | return SR_ERR; |
468 | } else { | |
469 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", | |
470 | ch->index + 1) != SR_OK) | |
471 | return SR_ERR; | |
472 | } | |
677f85d0 | 473 | if (devc->data_source != DATA_SOURCE_LIVE) { |
38354d9d | 474 | if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK) |
677f85d0 | 475 | return SR_ERR; |
38354d9d | 476 | if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK) |
677f85d0 | 477 | return SR_ERR; |
aff00e40 | 478 | } |
702f42e8 ML |
479 | break; |
480 | case PROTOCOL_V4: | |
e4204b17 | 481 | case PROTOCOL_V5: |
702f42e8 ML |
482 | if (ch->type == SR_CHANNEL_ANALOG) { |
483 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", | |
484 | ch->index + 1) != SR_OK) | |
485 | return SR_ERR; | |
486 | } else { | |
487 | if (rigol_ds_config_set(sdi, ":WAV:SOUR D%d", | |
488 | ch->index) != SR_OK) | |
489 | return SR_ERR; | |
490 | } | |
491 | ||
492 | if (rigol_ds_config_set(sdi, | |
493 | devc->data_source == DATA_SOURCE_LIVE ? | |
494 | ":WAV:MODE NORM" :":WAV:MODE RAW") != SR_OK) | |
495 | return SR_ERR; | |
496 | break; | |
497 | } | |
498 | ||
499 | if (devc->model->series->protocol >= PROTOCOL_V3 && | |
500 | ch->type == SR_CHANNEL_ANALOG) { | |
8cd15dd4 UH |
501 | /* Vertical increment. */ |
502 | if (sr_scpi_get_float(sdi->conn, ":WAV:YINC?", | |
503 | &devc->vert_inc[ch->index]) != SR_OK) | |
504 | return SR_ERR; | |
505 | /* Vertical origin. */ | |
506 | if (sr_scpi_get_float(sdi->conn, ":WAV:YOR?", | |
507 | &devc->vert_origin[ch->index]) != SR_OK) | |
508 | return SR_ERR; | |
702f42e8 ML |
509 | /* Vertical reference. */ |
510 | if (sr_scpi_get_int(sdi->conn, ":WAV:YREF?", | |
511 | &devc->vert_reference[ch->index]) != SR_OK) | |
512 | return SR_ERR; | |
8cd15dd4 UH |
513 | } else if (ch->type == SR_CHANNEL_ANALOG) { |
514 | devc->vert_inc[ch->index] = devc->vdiv[ch->index] / 25.6; | |
677f85d0 | 515 | } |
babab622 | 516 | |
aff00e40 ML |
517 | rigol_ds_set_wait_event(devc, WAIT_BLOCK); |
518 | ||
f76c24f6 | 519 | devc->num_channel_bytes = 0; |
aff00e40 | 520 | devc->num_header_bytes = 0; |
babab622 ML |
521 | devc->num_block_bytes = 0; |
522 | ||
523 | return SR_OK; | |
524 | } | |
525 | ||
526 | /* Read the header of a data block */ | |
aff00e40 | 527 | static int rigol_ds_read_header(struct sr_dev_inst *sdi) |
bafd4890 | 528 | { |
aff00e40 ML |
529 | struct sr_scpi_dev_inst *scpi = sdi->conn; |
530 | struct dev_context *devc = sdi->priv; | |
531 | char *buf = (char *) devc->buffer; | |
fe0d9caa ML |
532 | size_t header_length; |
533 | int ret; | |
aff00e40 ML |
534 | |
535 | /* Try to read the hashsign and length digit. */ | |
536 | if (devc->num_header_bytes < 2) { | |
fe0d9caa | 537 | ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes, |
aff00e40 | 538 | 2 - devc->num_header_bytes); |
fe0d9caa | 539 | if (ret < 0) { |
aff00e40 ML |
540 | sr_err("Read error while reading data header."); |
541 | return SR_ERR; | |
542 | } | |
fe0d9caa | 543 | devc->num_header_bytes += ret; |
bafd4890 | 544 | } |
aff00e40 ML |
545 | |
546 | if (devc->num_header_bytes < 2) | |
547 | return 0; | |
548 | ||
549 | if (buf[0] != '#' || !isdigit(buf[1]) || buf[1] == '0') { | |
550 | sr_err("Received invalid data block header '%c%c'.", buf[0], buf[1]); | |
551 | return SR_ERR; | |
bafd4890 | 552 | } |
bafd4890 | 553 | |
fe0d9caa | 554 | header_length = 2 + buf[1] - '0'; |
aff00e40 ML |
555 | |
556 | /* Try to read the length. */ | |
fe0d9caa ML |
557 | if (devc->num_header_bytes < header_length) { |
558 | ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes, | |
559 | header_length - devc->num_header_bytes); | |
560 | if (ret < 0) { | |
aff00e40 ML |
561 | sr_err("Read error while reading data header."); |
562 | return SR_ERR; | |
563 | } | |
fe0d9caa | 564 | devc->num_header_bytes += ret; |
bafd4890 | 565 | } |
aff00e40 | 566 | |
fe0d9caa | 567 | if (devc->num_header_bytes < header_length) |
aff00e40 ML |
568 | return 0; |
569 | ||
570 | /* Read the data length. */ | |
fe0d9caa | 571 | buf[header_length] = '\0'; |
aff00e40 | 572 | |
fe0d9caa | 573 | if (parse_int(buf + 2, &ret) != SR_OK) { |
aff00e40 | 574 | sr_err("Received invalid data block length '%s'.", buf + 2); |
bafd4890 ML |
575 | return -1; |
576 | } | |
577 | ||
fe0d9caa | 578 | sr_dbg("Received data block header: '%s' -> block length %d", buf, ret); |
bafd4890 | 579 | |
fe0d9caa | 580 | return ret; |
bafd4890 ML |
581 | } |
582 | ||
3086efdd | 583 | SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data) |
f4816ac6 | 584 | { |
e0b7d23c | 585 | struct sr_dev_inst *sdi; |
ae1bc1cc | 586 | struct sr_scpi_dev_inst *scpi; |
f4816ac6 | 587 | struct dev_context *devc; |
e0b7d23c | 588 | struct sr_datafeed_packet packet; |
246399f7 UH |
589 | struct sr_datafeed_analog analog; |
590 | struct sr_analog_encoding encoding; | |
591 | struct sr_analog_meaning meaning; | |
592 | struct sr_analog_spec spec; | |
6bb192bc | 593 | struct sr_datafeed_logic logic; |
8cd15dd4 | 594 | double vdiv, offset, origin; |
f80a0bf2 | 595 | int len, i, vref; |
ba7dd8bb | 596 | struct sr_channel *ch; |
bac11aeb | 597 | gsize expected_data_bytes; |
f4816ac6 | 598 | |
decfe89d | 599 | (void)fd; |
9bd4c956 | 600 | |
f4816ac6 ML |
601 | if (!(sdi = cb_data)) |
602 | return TRUE; | |
603 | ||
604 | if (!(devc = sdi->priv)) | |
605 | return TRUE; | |
606 | ||
ae1bc1cc | 607 | scpi = sdi->conn; |
9bd4c956 | 608 | |
dc89faea UH |
609 | if (!(revents == G_IO_IN || revents == 0)) |
610 | return TRUE; | |
611 | ||
612 | switch (devc->wait_event) { | |
613 | case WAIT_NONE: | |
614 | break; | |
615 | case WAIT_TRIGGER: | |
616 | if (rigol_ds_trigger_wait(sdi) != SR_OK) | |
3918fbb0 | 617 | return TRUE; |
dc89faea | 618 | if (rigol_ds_channel_start(sdi) != SR_OK) |
e086b750 | 619 | return TRUE; |
dc89faea UH |
620 | return TRUE; |
621 | case WAIT_BLOCK: | |
622 | if (rigol_ds_block_wait(sdi) != SR_OK) | |
623 | return TRUE; | |
624 | break; | |
625 | case WAIT_STOP: | |
626 | if (rigol_ds_stop_wait(sdi) != SR_OK) | |
627 | return TRUE; | |
628 | if (rigol_ds_check_stop(sdi) != SR_OK) | |
629 | return TRUE; | |
630 | if (rigol_ds_channel_start(sdi) != SR_OK) | |
631 | return TRUE; | |
632 | return TRUE; | |
633 | default: | |
634 | sr_err("BUG: Unknown event target encountered"); | |
635 | break; | |
636 | } | |
f76c24f6 | 637 | |
dc89faea | 638 | ch = devc->channel_entry->data; |
702f42e8 | 639 | |
dc89faea UH |
640 | expected_data_bytes = ch->type == SR_CHANNEL_ANALOG ? |
641 | devc->analog_frame_size : devc->digital_frame_size; | |
bac11aeb | 642 | |
dc89faea UH |
643 | if (devc->num_block_bytes == 0) { |
644 | if (devc->model->series->protocol >= PROTOCOL_V4) { | |
ef7fb1ab | 645 | if (rigol_ds_config_set(sdi, ":WAV:START %d", |
dc89faea UH |
646 | devc->num_channel_bytes + 1) != SR_OK) |
647 | return TRUE; | |
ef7fb1ab | 648 | if (rigol_ds_config_set(sdi, ":WAV:STOP %d", |
dc89faea UH |
649 | MIN(devc->num_channel_bytes + ACQ_BLOCK_SIZE, |
650 | devc->analog_frame_size)) != SR_OK) | |
05c644ea | 651 | return TRUE; |
bafd4890 | 652 | } |
f80a0bf2 | 653 | |
dc89faea UH |
654 | if (devc->model->series->protocol >= PROTOCOL_V3) |
655 | if (sr_scpi_send(sdi->conn, ":WAV:DATA?") != SR_OK) | |
656 | return TRUE; | |
f80a0bf2 | 657 | |
dc89faea | 658 | if (sr_scpi_read_begin(scpi) != SR_OK) |
7d63347e | 659 | return TRUE; |
6bb192bc | 660 | |
dc89faea UH |
661 | if (devc->format == FORMAT_IEEE488_2) { |
662 | sr_dbg("New block header expected"); | |
663 | len = rigol_ds_read_header(sdi); | |
664 | if (len == 0) | |
665 | /* Still reading the header. */ | |
666 | return TRUE; | |
667 | if (len == -1) { | |
8cd15dd4 | 668 | sr_err("Error while reading block header, aborting capture."); |
7d63347e | 669 | packet.type = SR_DF_FRAME_END; |
695dc859 | 670 | sr_session_send(sdi, &packet); |
8cd15dd4 | 671 | sr_dev_acquisition_stop(sdi); |
3ed7a40c ML |
672 | return TRUE; |
673 | } | |
dc89faea UH |
674 | /* At slow timebases in live capture the DS2072 |
675 | * sometimes returns "short" data blocks, with | |
676 | * apparently no way to get the rest of the data. | |
677 | * Discard these, the complete data block will | |
678 | * appear eventually. | |
679 | */ | |
680 | if (devc->data_source == DATA_SOURCE_LIVE | |
681 | && (unsigned)len < expected_data_bytes) { | |
682 | sr_dbg("Discarding short data block"); | |
683 | sr_scpi_read_data(scpi, (char *)devc->buffer, len + 1); | |
684 | return TRUE; | |
685 | } | |
686 | devc->num_block_bytes = len; | |
48460c6f | 687 | } else { |
dc89faea | 688 | devc->num_block_bytes = expected_data_bytes; |
ee7e9bee | 689 | } |
dc89faea UH |
690 | devc->num_block_read = 0; |
691 | } | |
75d8a4e5 | 692 | |
dc89faea UH |
693 | len = devc->num_block_bytes - devc->num_block_read; |
694 | if (len > ACQ_BUFFER_SIZE) | |
695 | len = ACQ_BUFFER_SIZE; | |
696 | sr_dbg("Requesting read of %d bytes", len); | |
48460c6f | 697 | |
dc89faea | 698 | len = sr_scpi_read_data(scpi, (char *)devc->buffer, len); |
48460c6f | 699 | |
dc89faea | 700 | if (len == -1) { |
8cd15dd4 | 701 | sr_err("Error while reading block data, aborting capture."); |
dc89faea | 702 | packet.type = SR_DF_FRAME_END; |
695dc859 | 703 | sr_session_send(sdi, &packet); |
8cd15dd4 | 704 | sr_dev_acquisition_stop(sdi); |
dc89faea UH |
705 | return TRUE; |
706 | } | |
707 | ||
708 | sr_dbg("Received %d bytes.", len); | |
709 | ||
710 | devc->num_block_read += len; | |
711 | ||
712 | if (ch->type == SR_CHANNEL_ANALOG) { | |
713 | vref = devc->vert_reference[ch->index]; | |
8cd15dd4 UH |
714 | vdiv = devc->vert_inc[ch->index]; |
715 | origin = devc->vert_origin[ch->index]; | |
dc89faea UH |
716 | offset = devc->vert_offset[ch->index]; |
717 | if (devc->model->series->protocol >= PROTOCOL_V3) | |
718 | for (i = 0; i < len; i++) | |
8cd15dd4 | 719 | devc->data[i] = ((int)devc->buffer[i] - vref - origin) * vdiv; |
dc89faea UH |
720 | else |
721 | for (i = 0; i < len; i++) | |
722 | devc->data[i] = (128 - devc->buffer[i]) * vdiv - offset; | |
b8f07f42 AJ |
723 | float vdivlog = log10f(vdiv); |
724 | int digits = -(int)vdivlog + (vdivlog < 0.0); | |
725 | sr_analog_init(&analog, &encoding, &meaning, &spec, digits); | |
246399f7 | 726 | analog.meaning->channels = g_slist_append(NULL, ch); |
dc89faea UH |
727 | analog.num_samples = len; |
728 | analog.data = devc->data; | |
246399f7 UH |
729 | analog.meaning->mq = SR_MQ_VOLTAGE; |
730 | analog.meaning->unit = SR_UNIT_VOLT; | |
731 | analog.meaning->mqflags = 0; | |
732 | packet.type = SR_DF_ANALOG; | |
dc89faea | 733 | packet.payload = &analog; |
695dc859 | 734 | sr_session_send(sdi, &packet); |
246399f7 | 735 | g_slist_free(analog.meaning->channels); |
dc89faea UH |
736 | } else { |
737 | logic.length = len; | |
738 | // TODO: For the MSO1000Z series, we need a way to express that | |
739 | // this data is in fact just for a single channel, with the valid | |
740 | // data for that channel in the LSB of each byte. | |
e4204b17 | 741 | logic.unitsize = devc->model->series->protocol >= PROTOCOL_V4 ? 1 : 2; |
dc89faea UH |
742 | logic.data = devc->buffer; |
743 | packet.type = SR_DF_LOGIC; | |
744 | packet.payload = &logic; | |
695dc859 | 745 | sr_session_send(sdi, &packet); |
dc89faea UH |
746 | } |
747 | ||
748 | if (devc->num_block_read == devc->num_block_bytes) { | |
749 | sr_dbg("Block has been completed"); | |
750 | if (devc->model->series->protocol >= PROTOCOL_V3) { | |
751 | /* Discard the terminating linefeed */ | |
752 | sr_scpi_read_data(scpi, (char *)devc->buffer, 1); | |
753 | } | |
754 | if (devc->format == FORMAT_IEEE488_2) { | |
755 | /* Prepare for possible next block */ | |
756 | devc->num_header_bytes = 0; | |
757 | devc->num_block_bytes = 0; | |
babab622 | 758 | if (devc->data_source != DATA_SOURCE_LIVE) |
dc89faea | 759 | rigol_ds_set_wait_event(devc, WAIT_BLOCK); |
babab622 | 760 | } |
8cd15dd4 UH |
761 | /* End acquisition when data for all channels is acquired. */ |
762 | if (!sr_scpi_read_complete(scpi) && !devc->channel_entry->next) { | |
dc89faea | 763 | sr_err("Read should have been completed"); |
702f42e8 | 764 | packet.type = SR_DF_FRAME_END; |
695dc859 | 765 | sr_session_send(sdi, &packet); |
8cd15dd4 | 766 | sr_dev_acquisition_stop(sdi); |
dc89faea UH |
767 | return TRUE; |
768 | } | |
769 | devc->num_block_read = 0; | |
770 | } else { | |
6433156c DE |
771 | sr_dbg("%" PRIu64 " of %" PRIu64 " block bytes read", |
772 | devc->num_block_read, devc->num_block_bytes); | |
dc89faea | 773 | } |
f76c24f6 | 774 | |
dc89faea | 775 | devc->num_channel_bytes += len; |
f76c24f6 | 776 | |
dc89faea UH |
777 | if (devc->num_channel_bytes < expected_data_bytes) |
778 | /* Don't have the full data for this channel yet, re-run. */ | |
779 | return TRUE; | |
f76c24f6 | 780 | |
dc89faea UH |
781 | /* End of data for this channel. */ |
782 | if (devc->model->series->protocol == PROTOCOL_V3) { | |
783 | /* Signal end of data download to scope */ | |
784 | if (devc->data_source != DATA_SOURCE_LIVE) | |
785 | /* | |
786 | * This causes a query error, without it switching | |
787 | * to the next channel causes an error. Fun with | |
788 | * firmware... | |
789 | */ | |
790 | rigol_ds_config_set(sdi, ":WAV:END"); | |
791 | } | |
792 | ||
793 | if (devc->channel_entry->next) { | |
794 | /* We got the frame for this channel, now get the next channel. */ | |
795 | devc->channel_entry = devc->channel_entry->next; | |
796 | rigol_ds_channel_start(sdi); | |
797 | } else { | |
798 | /* Done with this frame. */ | |
799 | packet.type = SR_DF_FRAME_END; | |
695dc859 | 800 | sr_session_send(sdi, &packet); |
dc89faea UH |
801 | |
802 | if (++devc->num_frames == devc->limit_frames) { | |
803 | /* Last frame, stop capture. */ | |
8cd15dd4 | 804 | sr_dev_acquisition_stop(sdi); |
dc89faea UH |
805 | } else { |
806 | /* Get the next frame, starting with the first channel. */ | |
807 | devc->channel_entry = devc->enabled_channels; | |
808 | ||
809 | rigol_ds_capture_start(sdi); | |
810 | ||
811 | /* Start of next frame. */ | |
812 | packet.type = SR_DF_FRAME_BEGIN; | |
695dc859 | 813 | sr_session_send(sdi, &packet); |
75d8a4e5 | 814 | } |
f4816ac6 ML |
815 | } |
816 | ||
817 | return TRUE; | |
818 | } | |
e0b7d23c | 819 | |
3086efdd | 820 | SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi) |
254dd102 BV |
821 | { |
822 | struct dev_context *devc; | |
e264ebde | 823 | struct sr_channel *ch; |
98bfc474 | 824 | char *cmd; |
821fbcad ML |
825 | unsigned int i; |
826 | int res; | |
254dd102 BV |
827 | |
828 | devc = sdi->priv; | |
829 | ||
6bb192bc | 830 | /* Analog channel state. */ |
821fbcad ML |
831 | for (i = 0; i < devc->model->analog_channels; i++) { |
832 | cmd = g_strdup_printf(":CHAN%d:DISP?", i + 1); | |
98bfc474 | 833 | res = sr_scpi_get_bool(sdi->conn, cmd, &devc->analog_channels[i]); |
821fbcad ML |
834 | g_free(cmd); |
835 | if (res != SR_OK) | |
836 | return SR_ERR; | |
e264ebde AJ |
837 | ch = g_slist_nth_data(sdi->channels, i); |
838 | ch->enabled = devc->analog_channels[i]; | |
821fbcad ML |
839 | } |
840 | sr_dbg("Current analog channel state:"); | |
841 | for (i = 0; i < devc->model->analog_channels; i++) | |
842 | sr_dbg("CH%d %s", i + 1, devc->analog_channels[i] ? "on" : "off"); | |
6bb192bc ML |
843 | |
844 | /* Digital channel state. */ | |
bafd4890 | 845 | if (devc->model->has_digital) { |
702f42e8 | 846 | if (sr_scpi_get_bool(sdi->conn, |
01dd7a4c | 847 | devc->model->series->protocol >= PROTOCOL_V3 ? |
702f42e8 | 848 | ":LA:STAT?" : ":LA:DISP?", |
98bfc474 | 849 | &devc->la_enabled) != SR_OK) |
04e8e01e | 850 | return SR_ERR; |
04e8e01e ML |
851 | sr_dbg("Logic analyzer %s, current digital channel state:", |
852 | devc->la_enabled ? "enabled" : "disabled"); | |
effb9dd1 | 853 | for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) { |
e4204b17 UH |
854 | if (devc->model->series->protocol >= PROTOCOL_V5) |
855 | cmd = g_strdup_printf(":LA:DISP? D%d", i); | |
856 | else if (devc->model->series->protocol >= PROTOCOL_V3) | |
857 | cmd = g_strdup_printf(":LA:DIG%d:DISP?", i); | |
858 | else | |
859 | cmd = g_strdup_printf(":DIG%d:TURN?", i); | |
98bfc474 | 860 | res = sr_scpi_get_bool(sdi->conn, cmd, &devc->digital_channels[i]); |
6bb192bc ML |
861 | g_free(cmd); |
862 | if (res != SR_OK) | |
863 | return SR_ERR; | |
e264ebde AJ |
864 | ch = g_slist_nth_data(sdi->channels, i + devc->model->analog_channels); |
865 | ch->enabled = devc->digital_channels[i]; | |
bfaf112b | 866 | sr_dbg("D%d: %s", i, devc->digital_channels[i] ? "on" : "off"); |
6bb192bc ML |
867 | } |
868 | } | |
254dd102 BV |
869 | |
870 | /* Timebase. */ | |
334fbc2a | 871 | if (sr_scpi_get_float(sdi->conn, ":TIM:SCAL?", &devc->timebase) != SR_OK) |
254dd102 | 872 | return SR_ERR; |
bafd4890 | 873 | sr_dbg("Current timebase %g", devc->timebase); |
254dd102 | 874 | |
934cf6cf AJ |
875 | /* Probe attenuation. */ |
876 | for (i = 0; i < devc->model->analog_channels; i++) { | |
877 | cmd = g_strdup_printf(":CHAN%d:PROB?", i + 1); | |
878 | res = sr_scpi_get_float(sdi->conn, cmd, &devc->attenuation[i]); | |
879 | g_free(cmd); | |
880 | if (res != SR_OK) | |
881 | return SR_ERR; | |
882 | } | |
883 | sr_dbg("Current probe attenuation:"); | |
884 | for (i = 0; i < devc->model->analog_channels; i++) | |
885 | sr_dbg("CH%d %g", i + 1, devc->attenuation[i]); | |
886 | ||
8719638f AJ |
887 | /* Vertical gain and offset. */ |
888 | if (rigol_ds_get_dev_cfg_vertical(sdi) != SR_OK) | |
889 | return SR_ERR; | |
254dd102 BV |
890 | |
891 | /* Coupling. */ | |
821fbcad ML |
892 | for (i = 0; i < devc->model->analog_channels; i++) { |
893 | cmd = g_strdup_printf(":CHAN%d:COUP?", i + 1); | |
334fbc2a | 894 | res = sr_scpi_get_string(sdi->conn, cmd, &devc->coupling[i]); |
821fbcad ML |
895 | g_free(cmd); |
896 | if (res != SR_OK) | |
897 | return SR_ERR; | |
898 | } | |
899 | sr_dbg("Current coupling:"); | |
900 | for (i = 0; i < devc->model->analog_channels; i++) | |
901 | sr_dbg("CH%d %s", i + 1, devc->coupling[i]); | |
254dd102 BV |
902 | |
903 | /* Trigger source. */ | |
334fbc2a | 904 | if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SOUR?", &devc->trigger_source) != SR_OK) |
254dd102 BV |
905 | return SR_ERR; |
906 | sr_dbg("Current trigger source %s", devc->trigger_source); | |
907 | ||
908 | /* Horizontal trigger position. */ | |
8cd15dd4 UH |
909 | if (sr_scpi_get_float(sdi->conn, devc->model->cmds[CMD_GET_HORIZ_TRIGGERPOS].str, |
910 | &devc->horiz_triggerpos) != SR_OK) | |
254dd102 | 911 | return SR_ERR; |
bafd4890 | 912 | sr_dbg("Current horizontal trigger position %g", devc->horiz_triggerpos); |
254dd102 BV |
913 | |
914 | /* Trigger slope. */ | |
334fbc2a | 915 | if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SLOP?", &devc->trigger_slope) != SR_OK) |
254dd102 BV |
916 | return SR_ERR; |
917 | sr_dbg("Current trigger slope %s", devc->trigger_slope); | |
918 | ||
9ea62f2e AJ |
919 | /* Trigger level. */ |
920 | if (sr_scpi_get_float(sdi->conn, ":TRIG:EDGE:LEV?", &devc->trigger_level) != SR_OK) | |
921 | return SR_ERR; | |
922 | sr_dbg("Current trigger level %g", devc->trigger_level); | |
923 | ||
254dd102 BV |
924 | return SR_OK; |
925 | } | |
8719638f AJ |
926 | |
927 | SR_PRIV int rigol_ds_get_dev_cfg_vertical(const struct sr_dev_inst *sdi) | |
928 | { | |
929 | struct dev_context *devc; | |
930 | char *cmd; | |
931 | unsigned int i; | |
932 | int res; | |
933 | ||
934 | devc = sdi->priv; | |
935 | ||
936 | /* Vertical gain. */ | |
937 | for (i = 0; i < devc->model->analog_channels; i++) { | |
938 | cmd = g_strdup_printf(":CHAN%d:SCAL?", i + 1); | |
939 | res = sr_scpi_get_float(sdi->conn, cmd, &devc->vdiv[i]); | |
940 | g_free(cmd); | |
941 | if (res != SR_OK) | |
942 | return SR_ERR; | |
943 | } | |
944 | sr_dbg("Current vertical gain:"); | |
945 | for (i = 0; i < devc->model->analog_channels; i++) | |
946 | sr_dbg("CH%d %g", i + 1, devc->vdiv[i]); | |
947 | ||
948 | /* Vertical offset. */ | |
949 | for (i = 0; i < devc->model->analog_channels; i++) { | |
950 | cmd = g_strdup_printf(":CHAN%d:OFFS?", i + 1); | |
951 | res = sr_scpi_get_float(sdi->conn, cmd, &devc->vert_offset[i]); | |
952 | g_free(cmd); | |
953 | if (res != SR_OK) | |
954 | return SR_ERR; | |
955 | } | |
956 | sr_dbg("Current vertical offset:"); | |
957 | for (i = 0; i < devc->model->analog_channels; i++) | |
958 | sr_dbg("CH%d %g", i + 1, devc->vert_offset[i]); | |
959 | ||
960 | return SR_OK; | |
961 | } |