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f4816ac6 ML |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2012 Martin Ling <martin-git@earth.li> | |
88e429c9 | 5 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> |
bafd4890 | 6 | * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de> |
f4816ac6 ML |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include <stdlib.h> | |
e0b7d23c ML |
23 | #include <stdarg.h> |
24 | #include <unistd.h> | |
25 | #include <errno.h> | |
a3df166f | 26 | #include <string.h> |
254dd102 | 27 | #include <math.h> |
bafd4890 ML |
28 | #include <ctype.h> |
29 | #include <time.h> | |
f4816ac6 | 30 | #include <glib.h> |
c1aae900 | 31 | #include <libsigrok/libsigrok.h> |
f4816ac6 | 32 | #include "libsigrok-internal.h" |
5a1afc09 | 33 | #include "scpi.h" |
f4816ac6 ML |
34 | #include "protocol.h" |
35 | ||
bafd4890 ML |
36 | /* |
37 | * This is a unified protocol driver for the DS1000 and DS2000 series. | |
38 | * | |
39 | * DS1000 support tested with a Rigol DS1102D. | |
40 | * | |
41 | * DS2000 support tested with a Rigol DS2072 using firmware version 01.01.00.02. | |
42 | * | |
43 | * The Rigol DS2000 series scopes try to adhere to the IEEE 488.2 (I think) | |
44 | * standard. If you want to read it - it costs real money... | |
45 | * | |
46 | * Every response from the scope has a linefeed appended because the | |
47 | * standard says so. In principle this could be ignored because sending the | |
48 | * next command clears the output queue of the scope. This driver tries to | |
49 | * avoid doing that because it may cause an error being generated inside the | |
50 | * scope and who knows what bugs the firmware has WRT this. | |
51 | * | |
52 | * Waveform data is transferred in a format called "arbitrary block program | |
53 | * data" specified in IEEE 488.2. See Agilents programming manuals for their | |
54 | * 2000/3000 series scopes for a nice description. | |
55 | * | |
56 | * Each data block from the scope has a header, e.g. "#900000001400". | |
57 | * The '#' marks the start of a block. | |
58 | * Next is one ASCII decimal digit between 1 and 9, this gives the number of | |
59 | * ASCII decimal digits following. | |
60 | * Last are the ASCII decimal digits giving the number of bytes (not | |
61 | * samples!) in the block. | |
62 | * | |
63 | * After this header as many data bytes as indicated follow. | |
64 | * | |
65 | * Each data block has a trailing linefeed too. | |
66 | */ | |
67 | ||
bafd4890 ML |
68 | static int parse_int(const char *str, int *ret) |
69 | { | |
70 | char *e; | |
71 | long tmp; | |
72 | ||
73 | errno = 0; | |
74 | tmp = strtol(str, &e, 10); | |
75 | if (e == str || *e != '\0') { | |
76 | sr_dbg("Failed to parse integer: '%s'", str); | |
77 | return SR_ERR; | |
78 | } | |
79 | if (errno) { | |
80 | sr_dbg("Failed to parse integer: '%s', numerical overflow", str); | |
81 | return SR_ERR; | |
82 | } | |
83 | if (tmp > INT_MAX || tmp < INT_MIN) { | |
84 | sr_dbg("Failed to parse integer: '%s', value to large/small", str); | |
85 | return SR_ERR; | |
86 | } | |
87 | ||
88 | *ret = (int)tmp; | |
89 | return SR_OK; | |
90 | } | |
91 | ||
babab622 ML |
92 | /* Set the next event to wait for in rigol_ds_receive */ |
93 | static void rigol_ds_set_wait_event(struct dev_context *devc, enum wait_events event) | |
94 | { | |
95 | if (event == WAIT_STOP) | |
96 | devc->wait_status = 2; | |
97 | else | |
98 | devc->wait_status = 1; | |
99 | devc->wait_event = event; | |
100 | } | |
101 | ||
bafd4890 | 102 | /* |
babab622 ML |
103 | * Waiting for a event will return a timeout after 2 to 3 seconds in order |
104 | * to not block the application. | |
bafd4890 | 105 | */ |
babab622 | 106 | static int rigol_ds_event_wait(const struct sr_dev_inst *sdi, char status1, char status2) |
bafd4890 | 107 | { |
334fbc2a | 108 | char *buf; |
bafd4890 ML |
109 | struct dev_context *devc; |
110 | time_t start; | |
111 | ||
112 | if (!(devc = sdi->priv)) | |
113 | return SR_ERR; | |
114 | ||
115 | start = time(NULL); | |
116 | ||
117 | /* | |
118 | * Trigger status may return: | |
babab622 ML |
119 | * "TD" or "T'D" - triggered |
120 | * "AUTO" - autotriggered | |
121 | * "RUN" - running | |
122 | * "WAIT" - waiting for trigger | |
123 | * "STOP" - stopped | |
bafd4890 ML |
124 | */ |
125 | ||
babab622 | 126 | if (devc->wait_status == 1) { |
bafd4890 ML |
127 | do { |
128 | if (time(NULL) - start >= 3) { | |
129 | sr_dbg("Timeout waiting for trigger"); | |
130 | return SR_ERR_TIMEOUT; | |
131 | } | |
132 | ||
334fbc2a | 133 | if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK) |
bafd4890 | 134 | return SR_ERR; |
babab622 | 135 | } while (buf[0] == status1 || buf[0] == status2); |
bafd4890 | 136 | |
babab622 | 137 | devc->wait_status = 2; |
bafd4890 | 138 | } |
babab622 | 139 | if (devc->wait_status == 2) { |
bafd4890 ML |
140 | do { |
141 | if (time(NULL) - start >= 3) { | |
142 | sr_dbg("Timeout waiting for trigger"); | |
143 | return SR_ERR_TIMEOUT; | |
144 | } | |
145 | ||
334fbc2a | 146 | if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK) |
bafd4890 | 147 | return SR_ERR; |
babab622 | 148 | } while (buf[0] != status1 && buf[0] != status2); |
bafd4890 | 149 | |
babab622 | 150 | rigol_ds_set_wait_event(devc, WAIT_NONE); |
bafd4890 ML |
151 | } |
152 | ||
153 | return SR_OK; | |
154 | } | |
155 | ||
156 | /* | |
babab622 ML |
157 | * For live capture we need to wait for a new trigger event to ensure that |
158 | * sample data is not returned twice. | |
bafd4890 ML |
159 | * |
160 | * Unfortunately this will never really work because for sufficiently fast | |
babab622 | 161 | * timebases and trigger rates it just can't catch the status changes. |
bafd4890 ML |
162 | * |
163 | * What would be needed is a trigger event register with autoreset like the | |
164 | * Agilents have. The Rigols don't seem to have anything like this. | |
165 | * | |
166 | * The workaround is to only wait for the trigger when the timebase is slow | |
167 | * enough. Of course this means that for faster timebases sample data can be | |
babab622 ML |
168 | * returned multiple times, this effect is mitigated somewhat by sleeping |
169 | * for about one sweep time in that case. | |
bafd4890 | 170 | */ |
babab622 | 171 | static int rigol_ds_trigger_wait(const struct sr_dev_inst *sdi) |
bafd4890 ML |
172 | { |
173 | struct dev_context *devc; | |
babab622 | 174 | long s; |
bafd4890 ML |
175 | |
176 | if (!(devc = sdi->priv)) | |
177 | return SR_ERR; | |
178 | ||
babab622 ML |
179 | /* |
180 | * If timebase < 50 msecs/DIV just sleep about one sweep time except | |
181 | * for really fast sweeps. | |
182 | */ | |
c2b394d5 | 183 | if (devc->timebase < 0.0499) { |
babab622 ML |
184 | if (devc->timebase > 0.99e-6) { |
185 | /* | |
186 | * Timebase * num hor. divs * 85(%) * 1e6(usecs) / 100 | |
187 | * -> 85 percent of sweep time | |
188 | */ | |
569d4dbd | 189 | s = (devc->timebase * devc->model->series->num_horizontal_divs |
babab622 ML |
190 | * 85e6) / 100L; |
191 | sr_spew("Sleeping for %ld usecs instead of trigger-wait", s); | |
192 | g_usleep(s); | |
193 | } | |
194 | rigol_ds_set_wait_event(devc, WAIT_NONE); | |
195 | return SR_OK; | |
196 | } else { | |
197 | return rigol_ds_event_wait(sdi, 'T', 'A'); | |
198 | } | |
199 | } | |
bafd4890 | 200 | |
babab622 ML |
201 | /* Wait for scope to got to "Stop" in single shot mode */ |
202 | static int rigol_ds_stop_wait(const struct sr_dev_inst *sdi) | |
203 | { | |
204 | return rigol_ds_event_wait(sdi, 'S', 'S'); | |
205 | } | |
206 | ||
207 | /* Check that a single shot acquisition actually succeeded on the DS2000 */ | |
208 | static int rigol_ds_check_stop(const struct sr_dev_inst *sdi) | |
209 | { | |
210 | struct dev_context *devc; | |
ba7dd8bb | 211 | struct sr_channel *ch; |
babab622 ML |
212 | int tmp; |
213 | ||
214 | if (!(devc = sdi->priv)) | |
bafd4890 | 215 | return SR_ERR; |
babab622 | 216 | |
ba7dd8bb | 217 | ch = devc->channel_entry->data; |
821fbcad | 218 | |
702f42e8 | 219 | if (devc->model->series->protocol != PROTOCOL_V3) |
e086b750 ML |
220 | return SR_OK; |
221 | ||
38354d9d | 222 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", |
ba7dd8bb | 223 | ch->index + 1) != SR_OK) |
babab622 ML |
224 | return SR_ERR; |
225 | /* Check that the number of samples will be accepted */ | |
38354d9d | 226 | if (rigol_ds_config_set(sdi, ":WAV:POIN %d", devc->analog_frame_size) != SR_OK) |
babab622 | 227 | return SR_ERR; |
334fbc2a | 228 | if (sr_scpi_get_int(sdi->conn, "*ESR?", &tmp) != SR_OK) |
bafd4890 | 229 | return SR_ERR; |
babab622 ML |
230 | /* |
231 | * If we get an "Execution error" the scope went from "Single" to | |
232 | * "Stop" without actually triggering. There is no waveform | |
233 | * displayed and trying to download one will fail - the scope thinks | |
234 | * it has 1400 samples (like display memory) and the driver thinks | |
235 | * it has a different number of samples. | |
236 | * | |
237 | * In that case just try to capture something again. Might still | |
238 | * fail in interesting ways. | |
239 | * | |
240 | * Ain't firmware fun? | |
241 | */ | |
242 | if (tmp & 0x10) { | |
243 | sr_warn("Single shot acquisition failed, retrying..."); | |
244 | /* Sleep a bit, otherwise the single shot will often fail */ | |
1a46cc62 | 245 | g_usleep(500 * 1000); |
38354d9d | 246 | rigol_ds_config_set(sdi, ":SING"); |
babab622 | 247 | rigol_ds_set_wait_event(devc, WAIT_STOP); |
bafd4890 | 248 | return SR_ERR; |
babab622 | 249 | } |
bafd4890 | 250 | |
babab622 ML |
251 | return SR_OK; |
252 | } | |
bafd4890 | 253 | |
babab622 ML |
254 | /* Wait for enough data becoming available in scope output buffer */ |
255 | static int rigol_ds_block_wait(const struct sr_dev_inst *sdi) | |
256 | { | |
334fbc2a | 257 | char *buf; |
babab622 ML |
258 | struct dev_context *devc; |
259 | time_t start; | |
260 | int len; | |
261 | ||
262 | if (!(devc = sdi->priv)) | |
263 | return SR_ERR; | |
264 | ||
702f42e8 | 265 | if (devc->model->series->protocol == PROTOCOL_V3) { |
babab622 | 266 | |
4472867a ML |
267 | start = time(NULL); |
268 | ||
269 | do { | |
270 | if (time(NULL) - start >= 3) { | |
271 | sr_dbg("Timeout waiting for data block"); | |
272 | return SR_ERR_TIMEOUT; | |
273 | } | |
babab622 | 274 | |
4472867a ML |
275 | /* |
276 | * The scope copies data really slowly from sample | |
277 | * memory to its output buffer, so try not to bother | |
278 | * it too much with SCPI requests but don't wait too | |
279 | * long for short sample frame sizes. | |
280 | */ | |
1a46cc62 | 281 | g_usleep(devc->analog_frame_size < (15 * 1000) ? (100 * 1000) : (1000 * 1000)); |
4472867a ML |
282 | |
283 | /* "READ,nnnn" (still working) or "IDLE,nnnn" (finished) */ | |
284 | if (sr_scpi_get_string(sdi->conn, ":WAV:STAT?", &buf) != SR_OK) | |
285 | return SR_ERR; | |
286 | ||
287 | if (parse_int(buf + 5, &len) != SR_OK) | |
288 | return SR_ERR; | |
1a46cc62 | 289 | } while (buf[0] == 'R' && len < (1000 * 1000)); |
4472867a | 290 | } |
babab622 ML |
291 | |
292 | rigol_ds_set_wait_event(devc, WAIT_NONE); | |
293 | ||
294 | return SR_OK; | |
295 | } | |
296 | ||
38354d9d ML |
297 | /* Send a configuration setting. */ |
298 | SR_PRIV int rigol_ds_config_set(const struct sr_dev_inst *sdi, const char *format, ...) | |
299 | { | |
300 | struct dev_context *devc = sdi->priv; | |
301 | va_list args; | |
302 | int ret; | |
303 | ||
304 | va_start(args, format); | |
305 | ret = sr_scpi_send_variadic(sdi->conn, format, args); | |
306 | va_end(args); | |
307 | ||
308 | if (ret != SR_OK) | |
309 | return SR_ERR; | |
310 | ||
569d4dbd | 311 | if (devc->model->series->protocol == PROTOCOL_V2) { |
38354d9d ML |
312 | /* The DS1000 series needs this stupid delay, *OPC? doesn't work. */ |
313 | sr_spew("delay %dms", 100); | |
1a46cc62 | 314 | g_usleep(100 * 1000); |
38354d9d ML |
315 | return SR_OK; |
316 | } else { | |
317 | return sr_scpi_get_opc(sdi->conn); | |
318 | } | |
319 | } | |
320 | ||
babab622 ML |
321 | /* Start capturing a new frameset */ |
322 | SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi) | |
323 | { | |
324 | struct dev_context *devc; | |
e086b750 | 325 | gchar *trig_mode; |
702f42e8 | 326 | unsigned int num_channels, i, j; |
babab622 ML |
327 | |
328 | if (!(devc = sdi->priv)) | |
329 | return SR_ERR; | |
330 | ||
331 | sr_dbg("Starting data capture for frameset %lu of %lu", | |
332 | devc->num_frames + 1, devc->limit_frames); | |
333 | ||
569d4dbd ML |
334 | switch (devc->model->series->protocol) { |
335 | case PROTOCOL_V1: | |
336 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); | |
337 | break; | |
338 | case PROTOCOL_V2: | |
339 | if (devc->data_source == DATA_SOURCE_LIVE) { | |
340 | if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE NORMAL") != SR_OK) | |
e086b750 | 341 | return SR_ERR; |
569d4dbd | 342 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); |
e086b750 | 343 | } else { |
e086b750 ML |
344 | if (rigol_ds_config_set(sdi, ":STOP") != SR_OK) |
345 | return SR_ERR; | |
346 | if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE RAW") != SR_OK) | |
347 | return SR_ERR; | |
348 | if (sr_scpi_get_string(sdi->conn, ":TRIG:MODE?", &trig_mode) != SR_OK) | |
349 | return SR_ERR; | |
350 | if (rigol_ds_config_set(sdi, ":TRIG:%s:SWE SING", trig_mode) != SR_OK) | |
351 | return SR_ERR; | |
352 | if (rigol_ds_config_set(sdi, ":RUN") != SR_OK) | |
353 | return SR_ERR; | |
569d4dbd ML |
354 | rigol_ds_set_wait_event(devc, WAIT_STOP); |
355 | } | |
356 | break; | |
357 | case PROTOCOL_V3: | |
702f42e8 | 358 | case PROTOCOL_V4: |
569d4dbd ML |
359 | if (rigol_ds_config_set(sdi, ":WAV:FORM BYTE") != SR_OK) |
360 | return SR_ERR; | |
361 | if (devc->data_source == DATA_SOURCE_LIVE) { | |
362 | if (rigol_ds_config_set(sdi, ":WAV:MODE NORM") != SR_OK) | |
363 | return SR_ERR; | |
702f42e8 ML |
364 | devc->analog_frame_size = devc->model->series->live_samples; |
365 | devc->digital_frame_size = devc->model->series->live_samples; | |
569d4dbd | 366 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); |
e086b750 | 367 | } else { |
702f42e8 ML |
368 | if (devc->model->series->protocol == PROTOCOL_V3) { |
369 | if (rigol_ds_config_set(sdi, ":WAV:MODE RAW") != SR_OK) | |
370 | return SR_ERR; | |
371 | } else if (devc->model->series->protocol == PROTOCOL_V4) { | |
372 | num_channels = 0; | |
373 | ||
374 | /* Channels 3 and 4 are multiplexed with D0-7 and D8-15 */ | |
375 | for (i = 0; i < devc->model->analog_channels; i++) { | |
376 | if (devc->analog_channels[i]) { | |
377 | num_channels++; | |
378 | } else if (i >= 2 && devc->model->has_digital) { | |
379 | for (j = 0; j < 8; j++) { | |
380 | if (devc->digital_channels[8 * (i - 2) + j]) { | |
381 | num_channels++; | |
382 | break; | |
383 | } | |
384 | } | |
385 | } | |
386 | } | |
387 | ||
388 | devc->analog_frame_size = devc->digital_frame_size = | |
389 | num_channels == 1 ? | |
390 | devc->model->series->buffer_samples : | |
391 | num_channels == 2 ? | |
392 | devc->model->series->buffer_samples / 2 : | |
393 | devc->model->series->buffer_samples / 4; | |
394 | } | |
395 | ||
e086b750 ML |
396 | if (rigol_ds_config_set(sdi, ":SING") != SR_OK) |
397 | return SR_ERR; | |
569d4dbd | 398 | rigol_ds_set_wait_event(devc, WAIT_STOP); |
e086b750 | 399 | } |
569d4dbd | 400 | break; |
bafd4890 ML |
401 | } |
402 | ||
403 | return SR_OK; | |
404 | } | |
405 | ||
babab622 ML |
406 | /* Start reading data from the current channel */ |
407 | SR_PRIV int rigol_ds_channel_start(const struct sr_dev_inst *sdi) | |
408 | { | |
409 | struct dev_context *devc; | |
ba7dd8bb | 410 | struct sr_channel *ch; |
babab622 ML |
411 | |
412 | if (!(devc = sdi->priv)) | |
413 | return SR_ERR; | |
414 | ||
ba7dd8bb | 415 | ch = devc->channel_entry->data; |
821fbcad | 416 | |
ba7dd8bb | 417 | sr_dbg("Starting reading data from channel %d", ch->index + 1); |
babab622 | 418 | |
2ea67fc9 | 419 | switch (devc->model->series->protocol) { |
702f42e8 ML |
420 | case PROTOCOL_V1: |
421 | case PROTOCOL_V2: | |
3f239f08 | 422 | if (ch->type == SR_CHANNEL_LOGIC) { |
677f85d0 ML |
423 | if (sr_scpi_send(sdi->conn, ":WAV:DATA? DIG") != SR_OK) |
424 | return SR_ERR; | |
425 | } else { | |
821fbcad | 426 | if (sr_scpi_send(sdi->conn, ":WAV:DATA? CHAN%d", |
ba7dd8bb | 427 | ch->index + 1) != SR_OK) |
677f85d0 ML |
428 | return SR_ERR; |
429 | } | |
e086b750 | 430 | rigol_ds_set_wait_event(devc, WAIT_NONE); |
702f42e8 ML |
431 | break; |
432 | case PROTOCOL_V3: | |
38354d9d | 433 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", |
ba7dd8bb | 434 | ch->index + 1) != SR_OK) |
babab622 | 435 | return SR_ERR; |
677f85d0 | 436 | if (devc->data_source != DATA_SOURCE_LIVE) { |
38354d9d | 437 | if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK) |
677f85d0 | 438 | return SR_ERR; |
38354d9d | 439 | if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK) |
677f85d0 | 440 | return SR_ERR; |
aff00e40 | 441 | } |
702f42e8 ML |
442 | break; |
443 | case PROTOCOL_V4: | |
444 | if (ch->type == SR_CHANNEL_ANALOG) { | |
445 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", | |
446 | ch->index + 1) != SR_OK) | |
447 | return SR_ERR; | |
448 | } else { | |
449 | if (rigol_ds_config_set(sdi, ":WAV:SOUR D%d", | |
450 | ch->index) != SR_OK) | |
451 | return SR_ERR; | |
452 | } | |
453 | ||
454 | if (rigol_ds_config_set(sdi, | |
455 | devc->data_source == DATA_SOURCE_LIVE ? | |
456 | ":WAV:MODE NORM" :":WAV:MODE RAW") != SR_OK) | |
457 | return SR_ERR; | |
458 | break; | |
459 | } | |
460 | ||
461 | if (devc->model->series->protocol >= PROTOCOL_V3 && | |
462 | ch->type == SR_CHANNEL_ANALOG) { | |
463 | /* Vertical reference. */ | |
464 | if (sr_scpi_get_int(sdi->conn, ":WAV:YREF?", | |
465 | &devc->vert_reference[ch->index]) != SR_OK) | |
466 | return SR_ERR; | |
677f85d0 | 467 | } |
babab622 | 468 | |
aff00e40 ML |
469 | rigol_ds_set_wait_event(devc, WAIT_BLOCK); |
470 | ||
f76c24f6 | 471 | devc->num_channel_bytes = 0; |
aff00e40 | 472 | devc->num_header_bytes = 0; |
babab622 ML |
473 | devc->num_block_bytes = 0; |
474 | ||
475 | return SR_OK; | |
476 | } | |
477 | ||
478 | /* Read the header of a data block */ | |
aff00e40 | 479 | static int rigol_ds_read_header(struct sr_dev_inst *sdi) |
bafd4890 | 480 | { |
aff00e40 ML |
481 | struct sr_scpi_dev_inst *scpi = sdi->conn; |
482 | struct dev_context *devc = sdi->priv; | |
483 | char *buf = (char *) devc->buffer; | |
fe0d9caa ML |
484 | size_t header_length; |
485 | int ret; | |
aff00e40 ML |
486 | |
487 | /* Try to read the hashsign and length digit. */ | |
488 | if (devc->num_header_bytes < 2) { | |
fe0d9caa | 489 | ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes, |
aff00e40 | 490 | 2 - devc->num_header_bytes); |
fe0d9caa | 491 | if (ret < 0) { |
aff00e40 ML |
492 | sr_err("Read error while reading data header."); |
493 | return SR_ERR; | |
494 | } | |
fe0d9caa | 495 | devc->num_header_bytes += ret; |
bafd4890 | 496 | } |
aff00e40 ML |
497 | |
498 | if (devc->num_header_bytes < 2) | |
499 | return 0; | |
500 | ||
501 | if (buf[0] != '#' || !isdigit(buf[1]) || buf[1] == '0') { | |
502 | sr_err("Received invalid data block header '%c%c'.", buf[0], buf[1]); | |
503 | return SR_ERR; | |
bafd4890 | 504 | } |
bafd4890 | 505 | |
fe0d9caa | 506 | header_length = 2 + buf[1] - '0'; |
aff00e40 ML |
507 | |
508 | /* Try to read the length. */ | |
fe0d9caa ML |
509 | if (devc->num_header_bytes < header_length) { |
510 | ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes, | |
511 | header_length - devc->num_header_bytes); | |
512 | if (ret < 0) { | |
aff00e40 ML |
513 | sr_err("Read error while reading data header."); |
514 | return SR_ERR; | |
515 | } | |
fe0d9caa | 516 | devc->num_header_bytes += ret; |
bafd4890 | 517 | } |
aff00e40 | 518 | |
fe0d9caa | 519 | if (devc->num_header_bytes < header_length) |
aff00e40 ML |
520 | return 0; |
521 | ||
522 | /* Read the data length. */ | |
fe0d9caa | 523 | buf[header_length] = '\0'; |
aff00e40 | 524 | |
fe0d9caa | 525 | if (parse_int(buf + 2, &ret) != SR_OK) { |
aff00e40 | 526 | sr_err("Received invalid data block length '%s'.", buf + 2); |
bafd4890 ML |
527 | return -1; |
528 | } | |
529 | ||
fe0d9caa | 530 | sr_dbg("Received data block header: '%s' -> block length %d", buf, ret); |
bafd4890 | 531 | |
fe0d9caa | 532 | return ret; |
bafd4890 ML |
533 | } |
534 | ||
3086efdd | 535 | SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data) |
f4816ac6 | 536 | { |
e0b7d23c | 537 | struct sr_dev_inst *sdi; |
ae1bc1cc | 538 | struct sr_scpi_dev_inst *scpi; |
f4816ac6 | 539 | struct dev_context *devc; |
e0b7d23c ML |
540 | struct sr_datafeed_packet packet; |
541 | struct sr_datafeed_analog analog; | |
6bb192bc | 542 | struct sr_datafeed_logic logic; |
254dd102 | 543 | double vdiv, offset; |
f80a0bf2 | 544 | int len, i, vref; |
ba7dd8bb | 545 | struct sr_channel *ch; |
bac11aeb | 546 | gsize expected_data_bytes; |
f4816ac6 | 547 | |
decfe89d | 548 | (void)fd; |
9bd4c956 | 549 | |
f4816ac6 ML |
550 | if (!(sdi = cb_data)) |
551 | return TRUE; | |
552 | ||
553 | if (!(devc = sdi->priv)) | |
554 | return TRUE; | |
555 | ||
ae1bc1cc | 556 | scpi = sdi->conn; |
9bd4c956 | 557 | |
dc89faea UH |
558 | if (!(revents == G_IO_IN || revents == 0)) |
559 | return TRUE; | |
560 | ||
561 | switch (devc->wait_event) { | |
562 | case WAIT_NONE: | |
563 | break; | |
564 | case WAIT_TRIGGER: | |
565 | if (rigol_ds_trigger_wait(sdi) != SR_OK) | |
3918fbb0 | 566 | return TRUE; |
dc89faea | 567 | if (rigol_ds_channel_start(sdi) != SR_OK) |
e086b750 | 568 | return TRUE; |
dc89faea UH |
569 | return TRUE; |
570 | case WAIT_BLOCK: | |
571 | if (rigol_ds_block_wait(sdi) != SR_OK) | |
572 | return TRUE; | |
573 | break; | |
574 | case WAIT_STOP: | |
575 | if (rigol_ds_stop_wait(sdi) != SR_OK) | |
576 | return TRUE; | |
577 | if (rigol_ds_check_stop(sdi) != SR_OK) | |
578 | return TRUE; | |
579 | if (rigol_ds_channel_start(sdi) != SR_OK) | |
580 | return TRUE; | |
581 | return TRUE; | |
582 | default: | |
583 | sr_err("BUG: Unknown event target encountered"); | |
584 | break; | |
585 | } | |
f76c24f6 | 586 | |
dc89faea | 587 | ch = devc->channel_entry->data; |
702f42e8 | 588 | |
dc89faea UH |
589 | expected_data_bytes = ch->type == SR_CHANNEL_ANALOG ? |
590 | devc->analog_frame_size : devc->digital_frame_size; | |
bac11aeb | 591 | |
dc89faea UH |
592 | if (devc->num_block_bytes == 0) { |
593 | if (devc->model->series->protocol >= PROTOCOL_V4) { | |
594 | if (sr_scpi_send(sdi->conn, ":WAV:START %d", | |
595 | devc->num_channel_bytes + 1) != SR_OK) | |
596 | return TRUE; | |
597 | if (sr_scpi_send(sdi->conn, ":WAV:STOP %d", | |
598 | MIN(devc->num_channel_bytes + ACQ_BLOCK_SIZE, | |
599 | devc->analog_frame_size)) != SR_OK) | |
05c644ea | 600 | return TRUE; |
bafd4890 | 601 | } |
f80a0bf2 | 602 | |
dc89faea UH |
603 | if (devc->model->series->protocol >= PROTOCOL_V3) |
604 | if (sr_scpi_send(sdi->conn, ":WAV:DATA?") != SR_OK) | |
605 | return TRUE; | |
f80a0bf2 | 606 | |
dc89faea | 607 | if (sr_scpi_read_begin(scpi) != SR_OK) |
7d63347e | 608 | return TRUE; |
6bb192bc | 609 | |
dc89faea UH |
610 | if (devc->format == FORMAT_IEEE488_2) { |
611 | sr_dbg("New block header expected"); | |
612 | len = rigol_ds_read_header(sdi); | |
613 | if (len == 0) | |
614 | /* Still reading the header. */ | |
615 | return TRUE; | |
616 | if (len == -1) { | |
617 | sr_err("Read error, aborting capture."); | |
7d63347e ML |
618 | packet.type = SR_DF_FRAME_END; |
619 | sr_session_send(cb_data, &packet); | |
3ed7a40c ML |
620 | sdi->driver->dev_acquisition_stop(sdi, cb_data); |
621 | return TRUE; | |
622 | } | |
dc89faea UH |
623 | /* At slow timebases in live capture the DS2072 |
624 | * sometimes returns "short" data blocks, with | |
625 | * apparently no way to get the rest of the data. | |
626 | * Discard these, the complete data block will | |
627 | * appear eventually. | |
628 | */ | |
629 | if (devc->data_source == DATA_SOURCE_LIVE | |
630 | && (unsigned)len < expected_data_bytes) { | |
631 | sr_dbg("Discarding short data block"); | |
632 | sr_scpi_read_data(scpi, (char *)devc->buffer, len + 1); | |
633 | return TRUE; | |
634 | } | |
635 | devc->num_block_bytes = len; | |
48460c6f | 636 | } else { |
dc89faea | 637 | devc->num_block_bytes = expected_data_bytes; |
ee7e9bee | 638 | } |
dc89faea UH |
639 | devc->num_block_read = 0; |
640 | } | |
75d8a4e5 | 641 | |
dc89faea UH |
642 | len = devc->num_block_bytes - devc->num_block_read; |
643 | if (len > ACQ_BUFFER_SIZE) | |
644 | len = ACQ_BUFFER_SIZE; | |
645 | sr_dbg("Requesting read of %d bytes", len); | |
48460c6f | 646 | |
dc89faea | 647 | len = sr_scpi_read_data(scpi, (char *)devc->buffer, len); |
48460c6f | 648 | |
dc89faea UH |
649 | if (len == -1) { |
650 | sr_err("Read error, aborting capture."); | |
651 | packet.type = SR_DF_FRAME_END; | |
652 | sr_session_send(cb_data, &packet); | |
653 | sdi->driver->dev_acquisition_stop(sdi, cb_data); | |
654 | return TRUE; | |
655 | } | |
656 | ||
657 | sr_dbg("Received %d bytes.", len); | |
658 | ||
659 | devc->num_block_read += len; | |
660 | ||
661 | if (ch->type == SR_CHANNEL_ANALOG) { | |
662 | vref = devc->vert_reference[ch->index]; | |
663 | vdiv = devc->vdiv[ch->index] / 25.6; | |
664 | offset = devc->vert_offset[ch->index]; | |
665 | if (devc->model->series->protocol >= PROTOCOL_V3) | |
666 | for (i = 0; i < len; i++) | |
667 | devc->data[i] = ((int)devc->buffer[i] - vref) * vdiv - offset; | |
668 | else | |
669 | for (i = 0; i < len; i++) | |
670 | devc->data[i] = (128 - devc->buffer[i]) * vdiv - offset; | |
671 | analog.channels = g_slist_append(NULL, ch); | |
672 | analog.num_samples = len; | |
673 | analog.data = devc->data; | |
674 | analog.mq = SR_MQ_VOLTAGE; | |
675 | analog.unit = SR_UNIT_VOLT; | |
676 | analog.mqflags = 0; | |
677 | packet.type = SR_DF_ANALOG; | |
678 | packet.payload = &analog; | |
679 | sr_session_send(cb_data, &packet); | |
680 | g_slist_free(analog.channels); | |
681 | } else { | |
682 | logic.length = len; | |
683 | // TODO: For the MSO1000Z series, we need a way to express that | |
684 | // this data is in fact just for a single channel, with the valid | |
685 | // data for that channel in the LSB of each byte. | |
686 | logic.unitsize = devc->model->series->protocol == PROTOCOL_V4 ? 1 : 2; | |
687 | logic.data = devc->buffer; | |
688 | packet.type = SR_DF_LOGIC; | |
689 | packet.payload = &logic; | |
690 | sr_session_send(cb_data, &packet); | |
691 | } | |
692 | ||
693 | if (devc->num_block_read == devc->num_block_bytes) { | |
694 | sr_dbg("Block has been completed"); | |
695 | if (devc->model->series->protocol >= PROTOCOL_V3) { | |
696 | /* Discard the terminating linefeed */ | |
697 | sr_scpi_read_data(scpi, (char *)devc->buffer, 1); | |
698 | } | |
699 | if (devc->format == FORMAT_IEEE488_2) { | |
700 | /* Prepare for possible next block */ | |
701 | devc->num_header_bytes = 0; | |
702 | devc->num_block_bytes = 0; | |
babab622 | 703 | if (devc->data_source != DATA_SOURCE_LIVE) |
dc89faea | 704 | rigol_ds_set_wait_event(devc, WAIT_BLOCK); |
babab622 | 705 | } |
dc89faea UH |
706 | if (!sr_scpi_read_complete(scpi)) { |
707 | sr_err("Read should have been completed"); | |
702f42e8 ML |
708 | packet.type = SR_DF_FRAME_END; |
709 | sr_session_send(cb_data, &packet); | |
dc89faea UH |
710 | sdi->driver->dev_acquisition_stop(sdi, cb_data); |
711 | return TRUE; | |
712 | } | |
713 | devc->num_block_read = 0; | |
714 | } else { | |
715 | sr_dbg("%d of %d block bytes read", devc->num_block_read, devc->num_block_bytes); | |
716 | } | |
f76c24f6 | 717 | |
dc89faea | 718 | devc->num_channel_bytes += len; |
f76c24f6 | 719 | |
dc89faea UH |
720 | if (devc->num_channel_bytes < expected_data_bytes) |
721 | /* Don't have the full data for this channel yet, re-run. */ | |
722 | return TRUE; | |
f76c24f6 | 723 | |
dc89faea UH |
724 | /* End of data for this channel. */ |
725 | if (devc->model->series->protocol == PROTOCOL_V3) { | |
726 | /* Signal end of data download to scope */ | |
727 | if (devc->data_source != DATA_SOURCE_LIVE) | |
728 | /* | |
729 | * This causes a query error, without it switching | |
730 | * to the next channel causes an error. Fun with | |
731 | * firmware... | |
732 | */ | |
733 | rigol_ds_config_set(sdi, ":WAV:END"); | |
734 | } | |
735 | ||
736 | if (devc->channel_entry->next) { | |
737 | /* We got the frame for this channel, now get the next channel. */ | |
738 | devc->channel_entry = devc->channel_entry->next; | |
739 | rigol_ds_channel_start(sdi); | |
740 | } else { | |
741 | /* Done with this frame. */ | |
742 | packet.type = SR_DF_FRAME_END; | |
743 | sr_session_send(cb_data, &packet); | |
744 | ||
745 | if (++devc->num_frames == devc->limit_frames) { | |
746 | /* Last frame, stop capture. */ | |
747 | sdi->driver->dev_acquisition_stop(sdi, cb_data); | |
748 | } else { | |
749 | /* Get the next frame, starting with the first channel. */ | |
750 | devc->channel_entry = devc->enabled_channels; | |
751 | ||
752 | rigol_ds_capture_start(sdi); | |
753 | ||
754 | /* Start of next frame. */ | |
755 | packet.type = SR_DF_FRAME_BEGIN; | |
756 | sr_session_send(cb_data, &packet); | |
75d8a4e5 | 757 | } |
f4816ac6 ML |
758 | } |
759 | ||
760 | return TRUE; | |
761 | } | |
e0b7d23c | 762 | |
3086efdd | 763 | SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi) |
254dd102 BV |
764 | { |
765 | struct dev_context *devc; | |
98bfc474 | 766 | char *cmd; |
821fbcad ML |
767 | unsigned int i; |
768 | int res; | |
254dd102 BV |
769 | |
770 | devc = sdi->priv; | |
771 | ||
6bb192bc | 772 | /* Analog channel state. */ |
821fbcad ML |
773 | for (i = 0; i < devc->model->analog_channels; i++) { |
774 | cmd = g_strdup_printf(":CHAN%d:DISP?", i + 1); | |
98bfc474 | 775 | res = sr_scpi_get_bool(sdi->conn, cmd, &devc->analog_channels[i]); |
821fbcad ML |
776 | g_free(cmd); |
777 | if (res != SR_OK) | |
778 | return SR_ERR; | |
821fbcad ML |
779 | } |
780 | sr_dbg("Current analog channel state:"); | |
781 | for (i = 0; i < devc->model->analog_channels; i++) | |
782 | sr_dbg("CH%d %s", i + 1, devc->analog_channels[i] ? "on" : "off"); | |
6bb192bc ML |
783 | |
784 | /* Digital channel state. */ | |
bafd4890 | 785 | if (devc->model->has_digital) { |
702f42e8 ML |
786 | if (sr_scpi_get_bool(sdi->conn, |
787 | devc->model->series->protocol >= PROTOCOL_V4 ? | |
788 | ":LA:STAT?" : ":LA:DISP?", | |
98bfc474 | 789 | &devc->la_enabled) != SR_OK) |
04e8e01e | 790 | return SR_ERR; |
04e8e01e ML |
791 | sr_dbg("Logic analyzer %s, current digital channel state:", |
792 | devc->la_enabled ? "enabled" : "disabled"); | |
effb9dd1 | 793 | for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) { |
702f42e8 ML |
794 | cmd = g_strdup_printf( |
795 | devc->model->series->protocol >= PROTOCOL_V4 ? | |
796 | ":LA:DIG%d:DISP?" : ":DIG%d:TURN?", i); | |
98bfc474 | 797 | res = sr_scpi_get_bool(sdi->conn, cmd, &devc->digital_channels[i]); |
6bb192bc ML |
798 | g_free(cmd); |
799 | if (res != SR_OK) | |
800 | return SR_ERR; | |
bfaf112b | 801 | sr_dbg("D%d: %s", i, devc->digital_channels[i] ? "on" : "off"); |
6bb192bc ML |
802 | } |
803 | } | |
254dd102 BV |
804 | |
805 | /* Timebase. */ | |
334fbc2a | 806 | if (sr_scpi_get_float(sdi->conn, ":TIM:SCAL?", &devc->timebase) != SR_OK) |
254dd102 | 807 | return SR_ERR; |
bafd4890 | 808 | sr_dbg("Current timebase %g", devc->timebase); |
254dd102 BV |
809 | |
810 | /* Vertical gain. */ | |
821fbcad ML |
811 | for (i = 0; i < devc->model->analog_channels; i++) { |
812 | cmd = g_strdup_printf(":CHAN%d:SCAL?", i + 1); | |
334fbc2a | 813 | res = sr_scpi_get_float(sdi->conn, cmd, &devc->vdiv[i]); |
821fbcad ML |
814 | g_free(cmd); |
815 | if (res != SR_OK) | |
816 | return SR_ERR; | |
817 | } | |
818 | sr_dbg("Current vertical gain:"); | |
819 | for (i = 0; i < devc->model->analog_channels; i++) | |
820 | sr_dbg("CH%d %g", i + 1, devc->vdiv[i]); | |
bafd4890 | 821 | |
254dd102 | 822 | /* Vertical offset. */ |
821fbcad ML |
823 | for (i = 0; i < devc->model->analog_channels; i++) { |
824 | cmd = g_strdup_printf(":CHAN%d:OFFS?", i + 1); | |
334fbc2a | 825 | res = sr_scpi_get_float(sdi->conn, cmd, &devc->vert_offset[i]); |
821fbcad ML |
826 | g_free(cmd); |
827 | if (res != SR_OK) | |
828 | return SR_ERR; | |
829 | } | |
830 | sr_dbg("Current vertical offset:"); | |
831 | for (i = 0; i < devc->model->analog_channels; i++) | |
832 | sr_dbg("CH%d %g", i + 1, devc->vert_offset[i]); | |
254dd102 BV |
833 | |
834 | /* Coupling. */ | |
821fbcad ML |
835 | for (i = 0; i < devc->model->analog_channels; i++) { |
836 | cmd = g_strdup_printf(":CHAN%d:COUP?", i + 1); | |
334fbc2a | 837 | res = sr_scpi_get_string(sdi->conn, cmd, &devc->coupling[i]); |
821fbcad ML |
838 | g_free(cmd); |
839 | if (res != SR_OK) | |
840 | return SR_ERR; | |
841 | } | |
842 | sr_dbg("Current coupling:"); | |
843 | for (i = 0; i < devc->model->analog_channels; i++) | |
844 | sr_dbg("CH%d %s", i + 1, devc->coupling[i]); | |
254dd102 BV |
845 | |
846 | /* Trigger source. */ | |
334fbc2a | 847 | if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SOUR?", &devc->trigger_source) != SR_OK) |
254dd102 BV |
848 | return SR_ERR; |
849 | sr_dbg("Current trigger source %s", devc->trigger_source); | |
850 | ||
851 | /* Horizontal trigger position. */ | |
334fbc2a | 852 | if (sr_scpi_get_float(sdi->conn, ":TIM:OFFS?", &devc->horiz_triggerpos) != SR_OK) |
254dd102 | 853 | return SR_ERR; |
bafd4890 | 854 | sr_dbg("Current horizontal trigger position %g", devc->horiz_triggerpos); |
254dd102 BV |
855 | |
856 | /* Trigger slope. */ | |
334fbc2a | 857 | if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SLOP?", &devc->trigger_slope) != SR_OK) |
254dd102 BV |
858 | return SR_ERR; |
859 | sr_dbg("Current trigger slope %s", devc->trigger_slope); | |
860 | ||
861 | return SR_OK; | |
862 | } |