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4bd80e12 | 1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
5 | * | |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 3 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
6ec6c43b | 20 | #include <config.h> |
4bd80e12 | 21 | #include "protocol.h" |
22 | ||
05199c0a | 23 | static const uint32_t drvopts[] = { |
4bd80e12 | 24 | SR_CONF_LOGIC_ANALYZER, |
05199c0a UH |
25 | }; |
26 | ||
27 | static const uint32_t devopts[] = { | |
5827f61b BV |
28 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
29 | SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
30 | SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, | |
31 | SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET, | |
32 | SR_CONF_PATTERN_MODE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
33 | SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET, | |
34 | SR_CONF_SWAP | SR_CONF_SET, | |
35 | SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET, | |
4bd80e12 | 36 | }; |
37 | ||
acc885c7 BV |
38 | static const int32_t trigger_matches[] = { |
39 | SR_TRIGGER_ZERO, | |
40 | SR_TRIGGER_ONE, | |
41 | SR_TRIGGER_RISING, | |
42 | SR_TRIGGER_FALLING, | |
43 | }; | |
44 | ||
4bd80e12 | 45 | #define STR_PATTERN_NONE "None" |
46 | #define STR_PATTERN_EXTERNAL "External" | |
47 | #define STR_PATTERN_INTERNAL "Internal" | |
48 | ||
49 | /* Supported methods of test pattern outputs */ | |
50 | enum { | |
51 | /** | |
52 | * Capture pins 31:16 (unbuffered wing) output a test pattern | |
53 | * that can captured on pins 0:15. | |
54 | */ | |
55 | PATTERN_EXTERNAL, | |
56 | ||
57 | /** Route test pattern internally to capture buffer. */ | |
58 | PATTERN_INTERNAL, | |
59 | }; | |
60 | ||
61 | static const char *patterns[] = { | |
62 | STR_PATTERN_NONE, | |
63 | STR_PATTERN_EXTERNAL, | |
64 | STR_PATTERN_INTERNAL, | |
65 | }; | |
66 | ||
67 | /* Channels are numbered 0-31 (on the PCB silkscreen). */ | |
53cda65a | 68 | SR_PRIV const char *p_ols_channel_names[] = { |
4bd80e12 | 69 | "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", |
70 | "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23", | |
71 | "24", "25", "26", "27", "28", "29", "30", "31", | |
4bd80e12 | 72 | }; |
73 | ||
74 | /* Default supported samplerates, can be overridden by device metadata. */ | |
75 | static const uint64_t samplerates[] = { | |
76 | SR_HZ(10), | |
77 | SR_MHZ(200), | |
78 | SR_HZ(1), | |
79 | }; | |
80 | ||
4f840ce9 | 81 | static GSList *scan(struct sr_dev_driver *di, GSList *options) |
4bd80e12 | 82 | { |
83 | struct sr_dev_inst *sdi; | |
4bd80e12 | 84 | struct dev_context *devc; |
85 | GSList *devices; | |
86 | int ret, i; | |
87 | char buf[70]; | |
88 | int bytes_read; | |
89 | ||
90 | (void)options; | |
91 | ||
4bd80e12 | 92 | devices = NULL; |
93 | ||
f57d8ffe | 94 | devc = g_malloc0(sizeof(struct dev_context)); |
4bd80e12 | 95 | |
b94cff40 | 96 | devc->max_samplebytes = devc->max_samplerate = devc->protocol_version = 0; |
4bd80e12 | 97 | |
4bd80e12 | 98 | devc->limit_samples = devc->capture_ratio = 0; |
99 | devc->trigger_at = -1; | |
100 | devc->channel_mask = 0xffffffff; | |
101 | devc->flag_reg = 0; | |
102 | ||
a95f142e | 103 | devc->ftdi_buf = g_malloc0(FTDI_BUF_SIZE); |
4bd80e12 | 104 | |
4bd80e12 | 105 | if (!(devc->ftdic = ftdi_new())) { |
106 | sr_err("Failed to initialize libftdi."); | |
107 | goto err_free_ftdi_buf;; | |
108 | } | |
109 | ||
ca314e06 | 110 | if (p_ols_open(devc) != SR_OK) |
4bd80e12 | 111 | goto err_free_ftdic; |
176d785d | 112 | |
4bd80e12 | 113 | /* The discovery procedure is like this: first send the Reset |
114 | * command (0x00) 5 times, since the device could be anywhere | |
115 | * in a 5-byte command. Then send the ID command (0x02). | |
116 | * If the device responds with 4 bytes ("OLS1" or "SLA1"), we | |
117 | * have a match. | |
118 | */ | |
119 | ||
120 | ret = SR_OK; | |
121 | for (i = 0; i < 5; i++) { | |
122 | if ((ret = write_shortcommand(devc, CMD_RESET)) != SR_OK) { | |
123 | break; | |
124 | } | |
125 | } | |
126 | if (ret != SR_OK) { | |
127 | sr_err("Could not reset device. Quitting."); | |
128 | goto err_close_ftdic; | |
129 | } | |
130 | write_shortcommand(devc, CMD_ID); | |
131 | ||
132 | /* Read the response data. */ | |
133 | bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 4); | |
134 | if (bytes_read < 0) { | |
135 | sr_err("Failed to read FTDI data (%d): %s.", | |
136 | bytes_read, ftdi_get_error_string(devc->ftdic)); | |
137 | goto err_close_ftdic; | |
138 | } | |
139 | if (bytes_read == 0) { | |
140 | goto err_close_ftdic; | |
141 | } | |
142 | ||
143 | if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4)) | |
144 | goto err_close_ftdic; | |
145 | ||
146 | /* Definitely using the OLS protocol, check if it supports | |
147 | * the metadata command. | |
148 | */ | |
149 | write_shortcommand(devc, CMD_METADATA); | |
150 | ||
151 | /* Read the metadata. */ | |
152 | bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 64); | |
153 | if (bytes_read < 0) { | |
154 | sr_err("Failed to read FTDI data (%d): %s.", | |
155 | bytes_read, ftdi_get_error_string(devc->ftdic)); | |
156 | goto err_close_ftdic; | |
157 | } | |
158 | if (bytes_read == 0) { | |
159 | goto err_close_ftdic; | |
160 | } | |
161 | ||
4bd80e12 | 162 | p_ols_close(devc); |
163 | ||
164 | /* Parse the metadata. */ | |
165 | sdi = p_ols_get_metadata((uint8_t *)buf, bytes_read, devc); | |
4bd80e12 | 166 | |
167 | /* Configure samplerate and divider. */ | |
168 | if (p_ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK) | |
169 | sr_dbg("Failed to set default samplerate (%"PRIu64").", | |
170 | DEFAULT_SAMPLERATE); | |
4bd80e12 | 171 | |
4bd80e12 | 172 | devices = g_slist_append(devices, sdi); |
173 | ||
15a5bfe4 | 174 | return std_scan_complete(di, devices); |
4bd80e12 | 175 | |
176 | err_close_ftdic: | |
177 | p_ols_close(devc); | |
178 | err_free_ftdic: | |
ca314e06 | 179 | ftdi_free(devc->ftdic); |
4bd80e12 | 180 | err_free_ftdi_buf: |
181 | g_free(devc->ftdi_buf); | |
4bd80e12 | 182 | g_free(devc); |
4bd80e12 | 183 | |
184 | return NULL; | |
185 | } | |
186 | ||
3553451f | 187 | static void clear_helper(struct dev_context *devc) |
4bd80e12 | 188 | { |
4bd80e12 | 189 | ftdi_free(devc->ftdic); |
190 | g_free(devc->ftdi_buf); | |
191 | } | |
192 | ||
4f840ce9 | 193 | static int dev_clear(const struct sr_dev_driver *di) |
4bd80e12 | 194 | { |
3553451f | 195 | return std_dev_clear_with_callback(di, (std_dev_clear_callback)clear_helper); |
4bd80e12 | 196 | } |
197 | ||
dd7a72ea UH |
198 | static int config_get(uint32_t key, GVariant **data, |
199 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
4bd80e12 | 200 | { |
201 | struct dev_context *devc; | |
202 | ||
203 | (void)cg; | |
204 | ||
205 | if (!sdi) | |
206 | return SR_ERR_ARG; | |
207 | ||
208 | devc = sdi->priv; | |
584560f1 | 209 | switch (key) { |
4bd80e12 | 210 | case SR_CONF_SAMPLERATE: |
211 | *data = g_variant_new_uint64(devc->cur_samplerate); | |
212 | break; | |
213 | case SR_CONF_CAPTURE_RATIO: | |
214 | *data = g_variant_new_uint64(devc->capture_ratio); | |
215 | break; | |
216 | case SR_CONF_LIMIT_SAMPLES: | |
217 | *data = g_variant_new_uint64(devc->limit_samples); | |
218 | break; | |
219 | case SR_CONF_PATTERN_MODE: | |
220 | if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE) | |
221 | *data = g_variant_new_string(STR_PATTERN_EXTERNAL); | |
222 | else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE) | |
223 | *data = g_variant_new_string(STR_PATTERN_INTERNAL); | |
224 | else | |
225 | *data = g_variant_new_string(STR_PATTERN_NONE); | |
226 | break; | |
227 | case SR_CONF_RLE: | |
228 | *data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE); | |
229 | break; | |
230 | case SR_CONF_EXTERNAL_CLOCK: | |
231 | *data = g_variant_new_boolean(devc->flag_reg & FLAG_CLOCK_EXTERNAL ? TRUE : FALSE); | |
232 | break; | |
233 | default: | |
234 | return SR_ERR_NA; | |
235 | } | |
236 | ||
237 | return SR_OK; | |
238 | } | |
239 | ||
dd7a72ea UH |
240 | static int config_set(uint32_t key, GVariant *data, |
241 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
4bd80e12 | 242 | { |
243 | struct dev_context *devc; | |
244 | uint16_t flag; | |
245 | uint64_t tmp_u64; | |
246 | int ret; | |
247 | const char *stropt; | |
248 | ||
249 | (void)cg; | |
250 | ||
4bd80e12 | 251 | devc = sdi->priv; |
252 | ||
584560f1 | 253 | switch (key) { |
4bd80e12 | 254 | case SR_CONF_SAMPLERATE: |
255 | tmp_u64 = g_variant_get_uint64(data); | |
256 | if (tmp_u64 < samplerates[0] || tmp_u64 > samplerates[1]) | |
257 | return SR_ERR_SAMPLERATE; | |
258 | ret = p_ols_set_samplerate(sdi, g_variant_get_uint64(data)); | |
259 | break; | |
260 | case SR_CONF_LIMIT_SAMPLES: | |
261 | tmp_u64 = g_variant_get_uint64(data); | |
262 | if (tmp_u64 < MIN_NUM_SAMPLES) | |
263 | return SR_ERR; | |
264 | devc->limit_samples = tmp_u64; | |
265 | ret = SR_OK; | |
266 | break; | |
267 | case SR_CONF_CAPTURE_RATIO: | |
268 | devc->capture_ratio = g_variant_get_uint64(data); | |
a5c38703 | 269 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) |
4bd80e12 | 270 | ret = SR_ERR; |
a5c38703 | 271 | else |
4bd80e12 | 272 | ret = SR_OK; |
273 | break; | |
274 | case SR_CONF_EXTERNAL_CLOCK: | |
275 | if (g_variant_get_boolean(data)) { | |
276 | sr_info("Enabling external clock."); | |
277 | devc->flag_reg |= FLAG_CLOCK_EXTERNAL; | |
278 | } else { | |
279 | sr_info("Disabled external clock."); | |
280 | devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL; | |
281 | } | |
282 | ret = SR_OK; | |
283 | break; | |
284 | case SR_CONF_PATTERN_MODE: | |
285 | stropt = g_variant_get_string(data, NULL); | |
286 | ret = SR_OK; | |
287 | flag = 0xffff; | |
288 | if (!strcmp(stropt, STR_PATTERN_NONE)) { | |
289 | sr_info("Disabling test modes."); | |
290 | flag = 0x0000; | |
291 | }else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) { | |
292 | sr_info("Enabling internal test mode."); | |
293 | flag = FLAG_INTERNAL_TEST_MODE; | |
294 | } else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) { | |
295 | sr_info("Enabling external test mode."); | |
296 | flag = FLAG_EXTERNAL_TEST_MODE; | |
297 | } else { | |
298 | ret = SR_ERR; | |
299 | } | |
300 | if (flag != 0xffff) { | |
301 | devc->flag_reg &= ~(FLAG_INTERNAL_TEST_MODE | FLAG_EXTERNAL_TEST_MODE); | |
302 | devc->flag_reg |= flag; | |
303 | } | |
304 | break; | |
305 | case SR_CONF_SWAP: | |
306 | if (g_variant_get_boolean(data)) { | |
307 | sr_info("Enabling channel swapping."); | |
308 | devc->flag_reg |= FLAG_SWAP_CHANNELS; | |
309 | } else { | |
310 | sr_info("Disabling channel swapping."); | |
311 | devc->flag_reg &= ~FLAG_SWAP_CHANNELS; | |
312 | } | |
313 | ret = SR_OK; | |
314 | break; | |
315 | ||
316 | case SR_CONF_RLE: | |
317 | if (g_variant_get_boolean(data)) { | |
318 | sr_info("Enabling RLE."); | |
319 | devc->flag_reg |= FLAG_RLE; | |
320 | } else { | |
321 | sr_info("Disabling RLE."); | |
322 | devc->flag_reg &= ~FLAG_RLE; | |
323 | } | |
324 | ret = SR_OK; | |
325 | break; | |
326 | default: | |
327 | ret = SR_ERR_NA; | |
328 | } | |
329 | ||
330 | return ret; | |
331 | } | |
332 | ||
dd7a72ea UH |
333 | static int config_list(uint32_t key, GVariant **data, |
334 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
4bd80e12 | 335 | { |
336 | struct dev_context *devc; | |
463160cb | 337 | GVariant *grange[2]; |
acc885c7 | 338 | int num_pols_changrp, i; |
4bd80e12 | 339 | |
4bd80e12 | 340 | switch (key) { |
341 | case SR_CONF_DEVICE_OPTIONS: | |
05199c0a | 342 | return STD_CONFIG_LIST(key, data, sdi, cg, NULL, drvopts, devopts); |
4bd80e12 | 343 | case SR_CONF_SAMPLERATE: |
53012da6 | 344 | *data = std_gvar_samplerates_steps(ARRAY_AND_SIZE(samplerates)); |
4bd80e12 | 345 | break; |
acc885c7 | 346 | case SR_CONF_TRIGGER_MATCH: |
53012da6 | 347 | *data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches)); |
4bd80e12 | 348 | break; |
349 | case SR_CONF_PATTERN_MODE: | |
53012da6 | 350 | *data = g_variant_new_strv(ARRAY_AND_SIZE(patterns)); |
4bd80e12 | 351 | break; |
352 | case SR_CONF_LIMIT_SAMPLES: | |
353 | if (!sdi) | |
354 | return SR_ERR_ARG; | |
355 | devc = sdi->priv; | |
356 | if (devc->flag_reg & FLAG_RLE) | |
357 | return SR_ERR_NA; | |
b94cff40 | 358 | if (devc->max_samplebytes == 0) |
4bd80e12 | 359 | /* Device didn't specify sample memory size in metadata. */ |
360 | return SR_ERR_NA; | |
361 | /* | |
362 | * Channel groups are turned off if no channels in that group are | |
363 | * enabled, making more room for samples for the enabled group. | |
364 | */ | |
acc885c7 BV |
365 | pols_channel_mask(sdi); |
366 | num_pols_changrp = 0; | |
4bd80e12 | 367 | for (i = 0; i < 4; i++) { |
368 | if (devc->channel_mask & (0xff << (i * 8))) | |
acc885c7 | 369 | num_pols_changrp++; |
4bd80e12 | 370 | } |
b94cff40 | 371 | /* 3 channel groups takes as many bytes as 4 channel groups */ |
acc885c7 BV |
372 | if (num_pols_changrp == 3) |
373 | num_pols_changrp = 4; | |
4bd80e12 | 374 | grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES); |
acc885c7 BV |
375 | if (num_pols_changrp) |
376 | grange[1] = g_variant_new_uint64(devc->max_samplebytes / num_pols_changrp); | |
377 | else | |
378 | grange[1] = g_variant_new_uint64(MIN_NUM_SAMPLES); | |
4bd80e12 | 379 | *data = g_variant_new_tuple(grange, 2); |
380 | break; | |
381 | default: | |
382 | return SR_ERR_NA; | |
383 | } | |
384 | ||
385 | return SR_OK; | |
386 | } | |
387 | ||
388 | static int dev_open(struct sr_dev_inst *sdi) | |
389 | { | |
390 | struct dev_context *devc; | |
4bd80e12 | 391 | |
392 | devc = sdi->priv; | |
393 | ||
7e463623 | 394 | return p_ols_open(devc); |
4bd80e12 | 395 | } |
396 | ||
397 | static int dev_close(struct sr_dev_inst *sdi) | |
398 | { | |
4bd80e12 | 399 | struct dev_context *devc; |
400 | ||
4bd80e12 | 401 | devc = sdi->priv; |
402 | ||
093e1cba | 403 | return p_ols_close(devc); |
4bd80e12 | 404 | } |
405 | ||
4bd80e12 | 406 | static int set_trigger(const struct sr_dev_inst *sdi, int stage) |
407 | { | |
408 | struct dev_context *devc; | |
409 | uint8_t cmd, arg[4]; | |
410 | ||
411 | devc = sdi->priv; | |
412 | ||
413 | cmd = CMD_SET_TRIGGER_MASK + stage * 4; | |
414 | arg[0] = devc->trigger_mask[stage] & 0xff; | |
415 | arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff; | |
416 | arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff; | |
417 | arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff; | |
418 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
419 | return SR_ERR; | |
420 | ||
421 | cmd = CMD_SET_TRIGGER_VALUE + stage * 4; | |
422 | arg[0] = devc->trigger_value[stage] & 0xff; | |
423 | arg[1] = (devc->trigger_value[stage] >> 8) & 0xff; | |
424 | arg[2] = (devc->trigger_value[stage] >> 16) & 0xff; | |
425 | arg[3] = (devc->trigger_value[stage] >> 24) & 0xff; | |
426 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
427 | return SR_ERR; | |
428 | ||
429 | cmd = CMD_SET_TRIGGER_CONFIG + stage * 4; | |
430 | arg[0] = arg[1] = arg[3] = 0x00; | |
431 | arg[2] = stage; | |
432 | if (stage == devc->num_stages) | |
433 | /* Last stage, fire when this one matches. */ | |
434 | arg[3] |= TRIGGER_START; | |
435 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
436 | return SR_ERR; | |
437 | ||
1e0de846 | 438 | cmd = CMD_SET_TRIGGER_EDGE + stage * 4; |
439 | arg[0] = devc->trigger_edge[stage] & 0xff; | |
440 | arg[1] = (devc->trigger_edge[stage] >> 8) & 0xff; | |
441 | arg[2] = (devc->trigger_edge[stage] >> 16) & 0xff; | |
442 | arg[3] = (devc->trigger_edge[stage] >> 24) & 0xff; | |
443 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
444 | return SR_ERR; | |
445 | ||
4bd80e12 | 446 | return SR_OK; |
447 | } | |
448 | ||
84cbaf77 BV |
449 | static int disable_trigger(const struct sr_dev_inst *sdi, int stage) |
450 | { | |
451 | struct dev_context *devc; | |
452 | uint8_t cmd, arg[4]; | |
453 | ||
454 | devc = sdi->priv; | |
455 | ||
456 | cmd = CMD_SET_TRIGGER_MASK + stage * 4; | |
457 | arg[0] = arg[1] = arg[2] = arg[3] = 0x00; | |
458 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
459 | return SR_ERR; | |
460 | ||
461 | cmd = CMD_SET_TRIGGER_VALUE + stage * 4; | |
462 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
463 | return SR_ERR; | |
464 | ||
465 | cmd = CMD_SET_TRIGGER_CONFIG + stage * 4; | |
466 | arg[2] = 0x03; | |
467 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
468 | return SR_ERR; | |
469 | ||
470 | cmd = CMD_SET_TRIGGER_EDGE + stage * 4; | |
471 | arg[2] = 0x00; | |
472 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
473 | return SR_ERR; | |
474 | ||
475 | return SR_OK; | |
476 | } | |
477 | ||
695dc859 | 478 | static int dev_acquisition_start(const struct sr_dev_inst *sdi) |
4bd80e12 | 479 | { |
480 | struct dev_context *devc; | |
481 | uint32_t samplecount, readcount, delaycount; | |
acc885c7 | 482 | uint8_t pols_changrp_mask, arg[4]; |
b94cff40 | 483 | uint16_t flag_tmp; |
acc885c7 | 484 | int num_pols_changrp, samplespercount; |
4bd80e12 | 485 | int ret, i; |
486 | ||
4bd80e12 | 487 | devc = sdi->priv; |
488 | ||
acc885c7 | 489 | pols_channel_mask(sdi); |
4bd80e12 | 490 | |
491 | /* | |
492 | * Enable/disable channel groups in the flag register according to the | |
acc885c7 BV |
493 | * channel mask. Calculate this here, because num_pols_changrp is |
494 | * needed to limit readcount. | |
4bd80e12 | 495 | */ |
acc885c7 BV |
496 | pols_changrp_mask = 0; |
497 | num_pols_changrp = 0; | |
4bd80e12 | 498 | for (i = 0; i < 4; i++) { |
499 | if (devc->channel_mask & (0xff << (i * 8))) { | |
acc885c7 BV |
500 | pols_changrp_mask |= (1 << i); |
501 | num_pols_changrp++; | |
4bd80e12 | 502 | } |
503 | } | |
b94cff40 | 504 | /* 3 channel groups takes as many bytes as 4 channel groups */ |
acc885c7 BV |
505 | if (num_pols_changrp == 3) |
506 | num_pols_changrp = 4; | |
b94cff40 | 507 | /* maximum number of samples (or RLE counts) the buffer memory can hold */ |
acc885c7 | 508 | devc->max_samples = devc->max_samplebytes / num_pols_changrp; |
4bd80e12 | 509 | |
510 | /* | |
511 | * Limit readcount to prevent reading past the end of the hardware | |
512 | * buffer. | |
513 | */ | |
514 | sr_dbg("max_samples = %d", devc->max_samples); | |
6433156c | 515 | sr_dbg("limit_samples = %" PRIu64, devc->limit_samples); |
b94cff40 | 516 | samplecount = MIN(devc->max_samples, devc->limit_samples); |
4bd80e12 | 517 | sr_dbg("Samplecount = %d", samplecount); |
518 | ||
b94cff40 | 519 | /* In demux mode the OLS is processing two samples per clock */ |
520 | if (devc->flag_reg & FLAG_DEMUX) { | |
521 | samplespercount = 8; | |
522 | } | |
523 | else { | |
524 | samplespercount = 4; | |
525 | } | |
526 | ||
527 | readcount = samplecount / samplespercount; | |
528 | ||
4bd80e12 | 529 | /* Rather read too many samples than too few. */ |
b94cff40 | 530 | if (samplecount % samplespercount != 0) |
4bd80e12 | 531 | readcount++; |
532 | ||
533 | /* Basic triggers. */ | |
acc885c7 BV |
534 | if (pols_convert_trigger(sdi) != SR_OK) { |
535 | sr_err("Failed to configure channels."); | |
536 | return SR_ERR; | |
537 | } | |
84cbaf77 | 538 | |
acc885c7 | 539 | if (devc->num_stages > 0) { |
4bd80e12 | 540 | delaycount = readcount * (1 - devc->capture_ratio / 100.0); |
b94cff40 | 541 | devc->trigger_at = (readcount - delaycount) * samplespercount - devc->num_stages; |
84cbaf77 BV |
542 | for (i = 0; i < NUM_TRIGGER_STAGES; i++) { |
543 | if (i <= devc->num_stages) { | |
544 | sr_dbg("Setting p-ols stage %d trigger.", i); | |
545 | if ((ret = set_trigger(sdi, i)) != SR_OK) | |
546 | return ret; | |
547 | } | |
548 | else { | |
549 | sr_dbg("Disabling p-ols stage %d trigger.", i); | |
550 | if ((ret = disable_trigger(sdi, i)) != SR_OK) | |
551 | return ret; | |
552 | } | |
4bd80e12 | 553 | } |
554 | } else { | |
555 | /* No triggers configured, force trigger on first stage. */ | |
556 | sr_dbg("Forcing trigger at stage 0."); | |
557 | if ((ret = set_trigger(sdi, 0)) != SR_OK) | |
558 | return ret; | |
559 | delaycount = readcount; | |
560 | } | |
561 | ||
562 | /* Samplerate. */ | |
563 | sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)", | |
564 | devc->cur_samplerate, devc->cur_samplerate_divider); | |
565 | arg[0] = devc->cur_samplerate_divider & 0xff; | |
566 | arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8; | |
567 | arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16; | |
568 | arg[3] = 0x00; | |
569 | if (write_longcommand(devc, CMD_SET_DIVIDER, arg) != SR_OK) | |
570 | return SR_ERR; | |
acc885c7 | 571 | |
4bd80e12 | 572 | /* Send extended sample limit and pre/post-trigger capture ratio. */ |
573 | arg[0] = ((readcount - 1) & 0xff); | |
574 | arg[1] = ((readcount - 1) & 0xff00) >> 8; | |
575 | arg[2] = ((readcount - 1) & 0xff0000) >> 16; | |
576 | arg[3] = ((readcount - 1) & 0xff000000) >> 24; | |
1e0de846 | 577 | if (write_longcommand(devc, CMD_CAPTURE_DELAY, arg) != SR_OK) |
4bd80e12 | 578 | return SR_ERR; |
579 | arg[0] = ((delaycount - 1) & 0xff); | |
580 | arg[1] = ((delaycount - 1) & 0xff00) >> 8; | |
581 | arg[2] = ((delaycount - 1) & 0xff0000) >> 16; | |
582 | arg[3] = ((delaycount - 1) & 0xff000000) >> 24; | |
1e0de846 | 583 | if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK) |
4bd80e12 | 584 | return SR_ERR; |
acc885c7 | 585 | |
4bd80e12 | 586 | /* Flag register. */ |
587 | sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s", | |
588 | devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off", | |
589 | devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off", | |
590 | devc->flag_reg & FLAG_RLE ? "on" : "off", | |
591 | devc->flag_reg & FLAG_FILTER ? "on": "off", | |
592 | devc->flag_reg & FLAG_DEMUX ? "on" : "off"); | |
593 | ||
b94cff40 | 594 | /* |
595 | * Enable/disable OLS channel groups in the flag register according | |
596 | * to the channel mask. 1 means "disable channel". | |
597 | */ | |
598 | devc->flag_reg &= ~0x3c; | |
acc885c7 | 599 | devc->flag_reg |= ~(pols_changrp_mask << 2) & 0x3c; |
b94cff40 | 600 | sr_dbg("flag_reg = %x", devc->flag_reg); |
601 | ||
602 | /* | |
176d785d UH |
603 | * In demux mode the OLS is processing two 8-bit or 16-bit samples |
604 | * in parallel and for this to work the lower two bits of the four | |
b94cff40 | 605 | * "channel_disable" bits must be replicated to the upper two bits. |
606 | */ | |
607 | flag_tmp = devc->flag_reg; | |
608 | if (devc->flag_reg & FLAG_DEMUX) { | |
609 | flag_tmp &= ~0x30; | |
acc885c7 | 610 | flag_tmp |= ~(pols_changrp_mask << 4) & 0x30; |
b94cff40 | 611 | } |
612 | arg[0] = flag_tmp & 0xff; | |
613 | arg[1] = flag_tmp >> 8; | |
4bd80e12 | 614 | arg[2] = arg[3] = 0x00; |
615 | if (write_longcommand(devc, CMD_SET_FLAGS, arg) != SR_OK) | |
616 | return SR_ERR; | |
617 | ||
618 | /* Start acquisition on the device. */ | |
619 | if (write_shortcommand(devc, CMD_RUN) != SR_OK) | |
620 | return SR_ERR; | |
621 | ||
622 | /* Reset all operational states. */ | |
623 | devc->rle_count = devc->num_transfers = 0; | |
624 | devc->num_samples = devc->num_bytes = 0; | |
625 | devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0; | |
626 | memset(devc->sample, 0, 4); | |
627 | ||
bee2b016 | 628 | std_session_send_df_header(sdi); |
4bd80e12 | 629 | |
630 | /* Hook up a dummy handler to receive data from the device. */ | |
c650d3ec | 631 | sr_session_source_add(sdi->session, -1, 0, 10, p_ols_receive_data, |
695dc859 | 632 | (struct sr_dev_inst *)sdi); |
4bd80e12 | 633 | |
634 | return SR_OK; | |
635 | } | |
636 | ||
695dc859 | 637 | static int dev_acquisition_stop(struct sr_dev_inst *sdi) |
4bd80e12 | 638 | { |
639 | struct dev_context *devc; | |
4bd80e12 | 640 | |
641 | devc = sdi->priv; | |
642 | ||
4bd80e12 | 643 | write_shortcommand(devc, CMD_RESET); |
644 | write_shortcommand(devc, CMD_RESET); | |
645 | write_shortcommand(devc, CMD_RESET); | |
646 | write_shortcommand(devc, CMD_RESET); | |
647 | write_shortcommand(devc, CMD_RESET); | |
648 | ||
dd7a4a71 | 649 | sr_session_source_remove(sdi->session, -1); |
4bd80e12 | 650 | |
bee2b016 | 651 | std_session_send_df_end(sdi); |
4bd80e12 | 652 | |
653 | return SR_OK; | |
654 | } | |
655 | ||
656 | SR_PRIV struct sr_dev_driver p_ols_driver_info = { | |
acc885c7 | 657 | .name = "p-ols", |
4bd80e12 | 658 | .longname = "Pipistrello OLS", |
659 | .api_version = 1, | |
c2fdcc25 | 660 | .init = std_init, |
700d6b64 | 661 | .cleanup = std_cleanup, |
4bd80e12 | 662 | .scan = scan, |
c01bf34c | 663 | .dev_list = std_dev_list, |
4bd80e12 | 664 | .dev_clear = dev_clear, |
665 | .config_get = config_get, | |
666 | .config_set = config_set, | |
667 | .config_list = config_list, | |
668 | .dev_open = dev_open, | |
669 | .dev_close = dev_close, | |
670 | .dev_acquisition_start = dev_acquisition_start, | |
671 | .dev_acquisition_stop = dev_acquisition_stop, | |
41812aca | 672 | .context = NULL, |
4bd80e12 | 673 | }; |
dd5c48a6 | 674 | SR_REGISTER_DEV_DRIVER(p_ols_driver_info); |