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4bd80e12 | 1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
5 | * | |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 3 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
6ec6c43b | 20 | #include <config.h> |
4bd80e12 | 21 | #include "protocol.h" |
22 | ||
f254bc4b | 23 | static const uint32_t devopts[] = { |
4bd80e12 | 24 | SR_CONF_LOGIC_ANALYZER, |
5827f61b BV |
25 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
26 | SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
27 | SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, | |
28 | SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET, | |
29 | SR_CONF_PATTERN_MODE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
30 | SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET, | |
31 | SR_CONF_SWAP | SR_CONF_SET, | |
32 | SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET, | |
4bd80e12 | 33 | }; |
34 | ||
acc885c7 BV |
35 | static const int32_t trigger_matches[] = { |
36 | SR_TRIGGER_ZERO, | |
37 | SR_TRIGGER_ONE, | |
38 | SR_TRIGGER_RISING, | |
39 | SR_TRIGGER_FALLING, | |
40 | }; | |
41 | ||
4bd80e12 | 42 | #define STR_PATTERN_NONE "None" |
43 | #define STR_PATTERN_EXTERNAL "External" | |
44 | #define STR_PATTERN_INTERNAL "Internal" | |
45 | ||
46 | /* Supported methods of test pattern outputs */ | |
47 | enum { | |
48 | /** | |
49 | * Capture pins 31:16 (unbuffered wing) output a test pattern | |
50 | * that can captured on pins 0:15. | |
51 | */ | |
52 | PATTERN_EXTERNAL, | |
53 | ||
54 | /** Route test pattern internally to capture buffer. */ | |
55 | PATTERN_INTERNAL, | |
56 | }; | |
57 | ||
58 | static const char *patterns[] = { | |
59 | STR_PATTERN_NONE, | |
60 | STR_PATTERN_EXTERNAL, | |
61 | STR_PATTERN_INTERNAL, | |
62 | }; | |
63 | ||
64 | /* Channels are numbered 0-31 (on the PCB silkscreen). */ | |
53cda65a | 65 | SR_PRIV const char *p_ols_channel_names[] = { |
4bd80e12 | 66 | "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", |
67 | "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23", | |
68 | "24", "25", "26", "27", "28", "29", "30", "31", | |
4bd80e12 | 69 | }; |
70 | ||
71 | /* Default supported samplerates, can be overridden by device metadata. */ | |
72 | static const uint64_t samplerates[] = { | |
73 | SR_HZ(10), | |
74 | SR_MHZ(200), | |
75 | SR_HZ(1), | |
76 | }; | |
77 | ||
4f840ce9 | 78 | static GSList *scan(struct sr_dev_driver *di, GSList *options) |
4bd80e12 | 79 | { |
80 | struct sr_dev_inst *sdi; | |
4bd80e12 | 81 | struct dev_context *devc; |
82 | GSList *devices; | |
83 | int ret, i; | |
84 | char buf[70]; | |
85 | int bytes_read; | |
86 | ||
87 | (void)options; | |
88 | ||
4bd80e12 | 89 | devices = NULL; |
90 | ||
91 | /* Allocate memory for our private device context. */ | |
f57d8ffe | 92 | devc = g_malloc0(sizeof(struct dev_context)); |
4bd80e12 | 93 | |
94 | /* Device-specific settings */ | |
b94cff40 | 95 | devc->max_samplebytes = devc->max_samplerate = devc->protocol_version = 0; |
4bd80e12 | 96 | |
97 | /* Acquisition settings */ | |
98 | devc->limit_samples = devc->capture_ratio = 0; | |
99 | devc->trigger_at = -1; | |
100 | devc->channel_mask = 0xffffffff; | |
101 | devc->flag_reg = 0; | |
102 | ||
103 | /* Allocate memory for the incoming ftdi data. */ | |
a95f142e | 104 | devc->ftdi_buf = g_malloc0(FTDI_BUF_SIZE); |
4bd80e12 | 105 | |
106 | /* Allocate memory for the FTDI context (ftdic) and initialize it. */ | |
107 | if (!(devc->ftdic = ftdi_new())) { | |
108 | sr_err("Failed to initialize libftdi."); | |
109 | goto err_free_ftdi_buf;; | |
110 | } | |
111 | ||
112 | /* Try to open the FTDI device */ | |
113 | if (p_ols_open(devc) != SR_OK) { | |
114 | goto err_free_ftdic; | |
115 | } | |
176d785d | 116 | |
4bd80e12 | 117 | /* The discovery procedure is like this: first send the Reset |
118 | * command (0x00) 5 times, since the device could be anywhere | |
119 | * in a 5-byte command. Then send the ID command (0x02). | |
120 | * If the device responds with 4 bytes ("OLS1" or "SLA1"), we | |
121 | * have a match. | |
122 | */ | |
123 | ||
124 | ret = SR_OK; | |
125 | for (i = 0; i < 5; i++) { | |
126 | if ((ret = write_shortcommand(devc, CMD_RESET)) != SR_OK) { | |
127 | break; | |
128 | } | |
129 | } | |
130 | if (ret != SR_OK) { | |
131 | sr_err("Could not reset device. Quitting."); | |
132 | goto err_close_ftdic; | |
133 | } | |
134 | write_shortcommand(devc, CMD_ID); | |
135 | ||
136 | /* Read the response data. */ | |
137 | bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 4); | |
138 | if (bytes_read < 0) { | |
139 | sr_err("Failed to read FTDI data (%d): %s.", | |
140 | bytes_read, ftdi_get_error_string(devc->ftdic)); | |
141 | goto err_close_ftdic; | |
142 | } | |
143 | if (bytes_read == 0) { | |
144 | goto err_close_ftdic; | |
145 | } | |
146 | ||
147 | if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4)) | |
148 | goto err_close_ftdic; | |
149 | ||
150 | /* Definitely using the OLS protocol, check if it supports | |
151 | * the metadata command. | |
152 | */ | |
153 | write_shortcommand(devc, CMD_METADATA); | |
154 | ||
155 | /* Read the metadata. */ | |
156 | bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 64); | |
157 | if (bytes_read < 0) { | |
158 | sr_err("Failed to read FTDI data (%d): %s.", | |
159 | bytes_read, ftdi_get_error_string(devc->ftdic)); | |
160 | goto err_close_ftdic; | |
161 | } | |
162 | if (bytes_read == 0) { | |
163 | goto err_close_ftdic; | |
164 | } | |
165 | ||
166 | /* Close device. We'll reopen it again when we need it. */ | |
167 | p_ols_close(devc); | |
168 | ||
169 | /* Parse the metadata. */ | |
170 | sdi = p_ols_get_metadata((uint8_t *)buf, bytes_read, devc); | |
4bd80e12 | 171 | |
172 | /* Configure samplerate and divider. */ | |
173 | if (p_ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK) | |
174 | sr_dbg("Failed to set default samplerate (%"PRIu64").", | |
175 | DEFAULT_SAMPLERATE); | |
4bd80e12 | 176 | |
4bd80e12 | 177 | devices = g_slist_append(devices, sdi); |
178 | ||
15a5bfe4 | 179 | return std_scan_complete(di, devices); |
4bd80e12 | 180 | |
181 | err_close_ftdic: | |
182 | p_ols_close(devc); | |
183 | err_free_ftdic: | |
184 | ftdi_free(devc->ftdic); /* NOT free() or g_free()! */ | |
185 | err_free_ftdi_buf: | |
186 | g_free(devc->ftdi_buf); | |
4bd80e12 | 187 | g_free(devc); |
4bd80e12 | 188 | |
189 | return NULL; | |
190 | } | |
191 | ||
3553451f | 192 | static void clear_helper(struct dev_context *devc) |
4bd80e12 | 193 | { |
4bd80e12 | 194 | ftdi_free(devc->ftdic); |
195 | g_free(devc->ftdi_buf); | |
196 | } | |
197 | ||
4f840ce9 | 198 | static int dev_clear(const struct sr_dev_driver *di) |
4bd80e12 | 199 | { |
3553451f | 200 | return std_dev_clear_with_callback(di, (std_dev_clear_callback)clear_helper); |
4bd80e12 | 201 | } |
202 | ||
584560f1 | 203 | static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi, |
4bd80e12 | 204 | const struct sr_channel_group *cg) |
205 | { | |
206 | struct dev_context *devc; | |
207 | ||
208 | (void)cg; | |
209 | ||
210 | if (!sdi) | |
211 | return SR_ERR_ARG; | |
212 | ||
213 | devc = sdi->priv; | |
584560f1 | 214 | switch (key) { |
4bd80e12 | 215 | case SR_CONF_SAMPLERATE: |
216 | *data = g_variant_new_uint64(devc->cur_samplerate); | |
217 | break; | |
218 | case SR_CONF_CAPTURE_RATIO: | |
219 | *data = g_variant_new_uint64(devc->capture_ratio); | |
220 | break; | |
221 | case SR_CONF_LIMIT_SAMPLES: | |
222 | *data = g_variant_new_uint64(devc->limit_samples); | |
223 | break; | |
224 | case SR_CONF_PATTERN_MODE: | |
225 | if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE) | |
226 | *data = g_variant_new_string(STR_PATTERN_EXTERNAL); | |
227 | else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE) | |
228 | *data = g_variant_new_string(STR_PATTERN_INTERNAL); | |
229 | else | |
230 | *data = g_variant_new_string(STR_PATTERN_NONE); | |
231 | break; | |
232 | case SR_CONF_RLE: | |
233 | *data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE); | |
234 | break; | |
235 | case SR_CONF_EXTERNAL_CLOCK: | |
236 | *data = g_variant_new_boolean(devc->flag_reg & FLAG_CLOCK_EXTERNAL ? TRUE : FALSE); | |
237 | break; | |
238 | default: | |
239 | return SR_ERR_NA; | |
240 | } | |
241 | ||
242 | return SR_OK; | |
243 | } | |
244 | ||
584560f1 | 245 | static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi, |
4bd80e12 | 246 | const struct sr_channel_group *cg) |
247 | { | |
248 | struct dev_context *devc; | |
249 | uint16_t flag; | |
250 | uint64_t tmp_u64; | |
251 | int ret; | |
252 | const char *stropt; | |
253 | ||
254 | (void)cg; | |
255 | ||
4bd80e12 | 256 | devc = sdi->priv; |
257 | ||
584560f1 | 258 | switch (key) { |
4bd80e12 | 259 | case SR_CONF_SAMPLERATE: |
260 | tmp_u64 = g_variant_get_uint64(data); | |
261 | if (tmp_u64 < samplerates[0] || tmp_u64 > samplerates[1]) | |
262 | return SR_ERR_SAMPLERATE; | |
263 | ret = p_ols_set_samplerate(sdi, g_variant_get_uint64(data)); | |
264 | break; | |
265 | case SR_CONF_LIMIT_SAMPLES: | |
266 | tmp_u64 = g_variant_get_uint64(data); | |
267 | if (tmp_u64 < MIN_NUM_SAMPLES) | |
268 | return SR_ERR; | |
269 | devc->limit_samples = tmp_u64; | |
270 | ret = SR_OK; | |
271 | break; | |
272 | case SR_CONF_CAPTURE_RATIO: | |
273 | devc->capture_ratio = g_variant_get_uint64(data); | |
a5c38703 | 274 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) |
4bd80e12 | 275 | ret = SR_ERR; |
a5c38703 | 276 | else |
4bd80e12 | 277 | ret = SR_OK; |
278 | break; | |
279 | case SR_CONF_EXTERNAL_CLOCK: | |
280 | if (g_variant_get_boolean(data)) { | |
281 | sr_info("Enabling external clock."); | |
282 | devc->flag_reg |= FLAG_CLOCK_EXTERNAL; | |
283 | } else { | |
284 | sr_info("Disabled external clock."); | |
285 | devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL; | |
286 | } | |
287 | ret = SR_OK; | |
288 | break; | |
289 | case SR_CONF_PATTERN_MODE: | |
290 | stropt = g_variant_get_string(data, NULL); | |
291 | ret = SR_OK; | |
292 | flag = 0xffff; | |
293 | if (!strcmp(stropt, STR_PATTERN_NONE)) { | |
294 | sr_info("Disabling test modes."); | |
295 | flag = 0x0000; | |
296 | }else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) { | |
297 | sr_info("Enabling internal test mode."); | |
298 | flag = FLAG_INTERNAL_TEST_MODE; | |
299 | } else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) { | |
300 | sr_info("Enabling external test mode."); | |
301 | flag = FLAG_EXTERNAL_TEST_MODE; | |
302 | } else { | |
303 | ret = SR_ERR; | |
304 | } | |
305 | if (flag != 0xffff) { | |
306 | devc->flag_reg &= ~(FLAG_INTERNAL_TEST_MODE | FLAG_EXTERNAL_TEST_MODE); | |
307 | devc->flag_reg |= flag; | |
308 | } | |
309 | break; | |
310 | case SR_CONF_SWAP: | |
311 | if (g_variant_get_boolean(data)) { | |
312 | sr_info("Enabling channel swapping."); | |
313 | devc->flag_reg |= FLAG_SWAP_CHANNELS; | |
314 | } else { | |
315 | sr_info("Disabling channel swapping."); | |
316 | devc->flag_reg &= ~FLAG_SWAP_CHANNELS; | |
317 | } | |
318 | ret = SR_OK; | |
319 | break; | |
320 | ||
321 | case SR_CONF_RLE: | |
322 | if (g_variant_get_boolean(data)) { | |
323 | sr_info("Enabling RLE."); | |
324 | devc->flag_reg |= FLAG_RLE; | |
325 | } else { | |
326 | sr_info("Disabling RLE."); | |
327 | devc->flag_reg &= ~FLAG_RLE; | |
328 | } | |
329 | ret = SR_OK; | |
330 | break; | |
331 | default: | |
332 | ret = SR_ERR_NA; | |
333 | } | |
334 | ||
335 | return ret; | |
336 | } | |
337 | ||
584560f1 | 338 | static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi, |
4bd80e12 | 339 | const struct sr_channel_group *cg) |
340 | { | |
341 | struct dev_context *devc; | |
342 | GVariant *gvar, *grange[2]; | |
343 | GVariantBuilder gvb; | |
acc885c7 | 344 | int num_pols_changrp, i; |
4bd80e12 | 345 | |
4bd80e12 | 346 | switch (key) { |
347 | case SR_CONF_DEVICE_OPTIONS: | |
e66d1892 | 348 | return STD_CONFIG_LIST(key, data, sdi, cg, NULL, NULL, devopts); |
4bd80e12 | 349 | case SR_CONF_SAMPLERATE: |
350 | g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}")); | |
351 | gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates, | |
352 | ARRAY_SIZE(samplerates), sizeof(uint64_t)); | |
353 | g_variant_builder_add(&gvb, "{sv}", "samplerate-steps", gvar); | |
354 | *data = g_variant_builder_end(&gvb); | |
355 | break; | |
acc885c7 BV |
356 | case SR_CONF_TRIGGER_MATCH: |
357 | *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32, | |
358 | trigger_matches, ARRAY_SIZE(trigger_matches), | |
359 | sizeof(int32_t)); | |
4bd80e12 | 360 | break; |
361 | case SR_CONF_PATTERN_MODE: | |
362 | *data = g_variant_new_strv(patterns, ARRAY_SIZE(patterns)); | |
363 | break; | |
364 | case SR_CONF_LIMIT_SAMPLES: | |
365 | if (!sdi) | |
366 | return SR_ERR_ARG; | |
367 | devc = sdi->priv; | |
368 | if (devc->flag_reg & FLAG_RLE) | |
369 | return SR_ERR_NA; | |
b94cff40 | 370 | if (devc->max_samplebytes == 0) |
4bd80e12 | 371 | /* Device didn't specify sample memory size in metadata. */ |
372 | return SR_ERR_NA; | |
373 | /* | |
374 | * Channel groups are turned off if no channels in that group are | |
375 | * enabled, making more room for samples for the enabled group. | |
376 | */ | |
acc885c7 BV |
377 | pols_channel_mask(sdi); |
378 | num_pols_changrp = 0; | |
4bd80e12 | 379 | for (i = 0; i < 4; i++) { |
380 | if (devc->channel_mask & (0xff << (i * 8))) | |
acc885c7 | 381 | num_pols_changrp++; |
4bd80e12 | 382 | } |
b94cff40 | 383 | /* 3 channel groups takes as many bytes as 4 channel groups */ |
acc885c7 BV |
384 | if (num_pols_changrp == 3) |
385 | num_pols_changrp = 4; | |
4bd80e12 | 386 | grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES); |
acc885c7 BV |
387 | if (num_pols_changrp) |
388 | grange[1] = g_variant_new_uint64(devc->max_samplebytes / num_pols_changrp); | |
389 | else | |
390 | grange[1] = g_variant_new_uint64(MIN_NUM_SAMPLES); | |
4bd80e12 | 391 | *data = g_variant_new_tuple(grange, 2); |
392 | break; | |
393 | default: | |
394 | return SR_ERR_NA; | |
395 | } | |
396 | ||
397 | return SR_OK; | |
398 | } | |
399 | ||
400 | static int dev_open(struct sr_dev_inst *sdi) | |
401 | { | |
402 | struct dev_context *devc; | |
4bd80e12 | 403 | |
404 | devc = sdi->priv; | |
405 | ||
7e463623 | 406 | return p_ols_open(devc); |
4bd80e12 | 407 | } |
408 | ||
409 | static int dev_close(struct sr_dev_inst *sdi) | |
410 | { | |
4bd80e12 | 411 | struct dev_context *devc; |
412 | ||
4bd80e12 | 413 | devc = sdi->priv; |
414 | ||
093e1cba | 415 | return p_ols_close(devc); |
4bd80e12 | 416 | } |
417 | ||
4bd80e12 | 418 | static int set_trigger(const struct sr_dev_inst *sdi, int stage) |
419 | { | |
420 | struct dev_context *devc; | |
421 | uint8_t cmd, arg[4]; | |
422 | ||
423 | devc = sdi->priv; | |
424 | ||
425 | cmd = CMD_SET_TRIGGER_MASK + stage * 4; | |
426 | arg[0] = devc->trigger_mask[stage] & 0xff; | |
427 | arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff; | |
428 | arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff; | |
429 | arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff; | |
430 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
431 | return SR_ERR; | |
432 | ||
433 | cmd = CMD_SET_TRIGGER_VALUE + stage * 4; | |
434 | arg[0] = devc->trigger_value[stage] & 0xff; | |
435 | arg[1] = (devc->trigger_value[stage] >> 8) & 0xff; | |
436 | arg[2] = (devc->trigger_value[stage] >> 16) & 0xff; | |
437 | arg[3] = (devc->trigger_value[stage] >> 24) & 0xff; | |
438 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
439 | return SR_ERR; | |
440 | ||
441 | cmd = CMD_SET_TRIGGER_CONFIG + stage * 4; | |
442 | arg[0] = arg[1] = arg[3] = 0x00; | |
443 | arg[2] = stage; | |
444 | if (stage == devc->num_stages) | |
445 | /* Last stage, fire when this one matches. */ | |
446 | arg[3] |= TRIGGER_START; | |
447 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
448 | return SR_ERR; | |
449 | ||
1e0de846 | 450 | cmd = CMD_SET_TRIGGER_EDGE + stage * 4; |
451 | arg[0] = devc->trigger_edge[stage] & 0xff; | |
452 | arg[1] = (devc->trigger_edge[stage] >> 8) & 0xff; | |
453 | arg[2] = (devc->trigger_edge[stage] >> 16) & 0xff; | |
454 | arg[3] = (devc->trigger_edge[stage] >> 24) & 0xff; | |
455 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
456 | return SR_ERR; | |
457 | ||
4bd80e12 | 458 | return SR_OK; |
459 | } | |
460 | ||
84cbaf77 BV |
461 | static int disable_trigger(const struct sr_dev_inst *sdi, int stage) |
462 | { | |
463 | struct dev_context *devc; | |
464 | uint8_t cmd, arg[4]; | |
465 | ||
466 | devc = sdi->priv; | |
467 | ||
468 | cmd = CMD_SET_TRIGGER_MASK + stage * 4; | |
469 | arg[0] = arg[1] = arg[2] = arg[3] = 0x00; | |
470 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
471 | return SR_ERR; | |
472 | ||
473 | cmd = CMD_SET_TRIGGER_VALUE + stage * 4; | |
474 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
475 | return SR_ERR; | |
476 | ||
477 | cmd = CMD_SET_TRIGGER_CONFIG + stage * 4; | |
478 | arg[2] = 0x03; | |
479 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
480 | return SR_ERR; | |
481 | ||
482 | cmd = CMD_SET_TRIGGER_EDGE + stage * 4; | |
483 | arg[2] = 0x00; | |
484 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
485 | return SR_ERR; | |
486 | ||
487 | return SR_OK; | |
488 | } | |
489 | ||
695dc859 | 490 | static int dev_acquisition_start(const struct sr_dev_inst *sdi) |
4bd80e12 | 491 | { |
492 | struct dev_context *devc; | |
493 | uint32_t samplecount, readcount, delaycount; | |
acc885c7 | 494 | uint8_t pols_changrp_mask, arg[4]; |
b94cff40 | 495 | uint16_t flag_tmp; |
acc885c7 | 496 | int num_pols_changrp, samplespercount; |
4bd80e12 | 497 | int ret, i; |
498 | ||
4bd80e12 | 499 | devc = sdi->priv; |
500 | ||
acc885c7 | 501 | pols_channel_mask(sdi); |
4bd80e12 | 502 | |
503 | /* | |
504 | * Enable/disable channel groups in the flag register according to the | |
acc885c7 BV |
505 | * channel mask. Calculate this here, because num_pols_changrp is |
506 | * needed to limit readcount. | |
4bd80e12 | 507 | */ |
acc885c7 BV |
508 | pols_changrp_mask = 0; |
509 | num_pols_changrp = 0; | |
4bd80e12 | 510 | for (i = 0; i < 4; i++) { |
511 | if (devc->channel_mask & (0xff << (i * 8))) { | |
acc885c7 BV |
512 | pols_changrp_mask |= (1 << i); |
513 | num_pols_changrp++; | |
4bd80e12 | 514 | } |
515 | } | |
b94cff40 | 516 | /* 3 channel groups takes as many bytes as 4 channel groups */ |
acc885c7 BV |
517 | if (num_pols_changrp == 3) |
518 | num_pols_changrp = 4; | |
b94cff40 | 519 | /* maximum number of samples (or RLE counts) the buffer memory can hold */ |
acc885c7 | 520 | devc->max_samples = devc->max_samplebytes / num_pols_changrp; |
4bd80e12 | 521 | |
522 | /* | |
523 | * Limit readcount to prevent reading past the end of the hardware | |
524 | * buffer. | |
525 | */ | |
526 | sr_dbg("max_samples = %d", devc->max_samples); | |
6433156c | 527 | sr_dbg("limit_samples = %" PRIu64, devc->limit_samples); |
b94cff40 | 528 | samplecount = MIN(devc->max_samples, devc->limit_samples); |
4bd80e12 | 529 | sr_dbg("Samplecount = %d", samplecount); |
530 | ||
b94cff40 | 531 | /* In demux mode the OLS is processing two samples per clock */ |
532 | if (devc->flag_reg & FLAG_DEMUX) { | |
533 | samplespercount = 8; | |
534 | } | |
535 | else { | |
536 | samplespercount = 4; | |
537 | } | |
538 | ||
539 | readcount = samplecount / samplespercount; | |
540 | ||
4bd80e12 | 541 | /* Rather read too many samples than too few. */ |
b94cff40 | 542 | if (samplecount % samplespercount != 0) |
4bd80e12 | 543 | readcount++; |
544 | ||
545 | /* Basic triggers. */ | |
acc885c7 BV |
546 | if (pols_convert_trigger(sdi) != SR_OK) { |
547 | sr_err("Failed to configure channels."); | |
548 | return SR_ERR; | |
549 | } | |
84cbaf77 | 550 | |
acc885c7 | 551 | if (devc->num_stages > 0) { |
4bd80e12 | 552 | delaycount = readcount * (1 - devc->capture_ratio / 100.0); |
b94cff40 | 553 | devc->trigger_at = (readcount - delaycount) * samplespercount - devc->num_stages; |
84cbaf77 BV |
554 | for (i = 0; i < NUM_TRIGGER_STAGES; i++) { |
555 | if (i <= devc->num_stages) { | |
556 | sr_dbg("Setting p-ols stage %d trigger.", i); | |
557 | if ((ret = set_trigger(sdi, i)) != SR_OK) | |
558 | return ret; | |
559 | } | |
560 | else { | |
561 | sr_dbg("Disabling p-ols stage %d trigger.", i); | |
562 | if ((ret = disable_trigger(sdi, i)) != SR_OK) | |
563 | return ret; | |
564 | } | |
4bd80e12 | 565 | } |
566 | } else { | |
567 | /* No triggers configured, force trigger on first stage. */ | |
568 | sr_dbg("Forcing trigger at stage 0."); | |
569 | if ((ret = set_trigger(sdi, 0)) != SR_OK) | |
570 | return ret; | |
571 | delaycount = readcount; | |
572 | } | |
573 | ||
574 | /* Samplerate. */ | |
575 | sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)", | |
576 | devc->cur_samplerate, devc->cur_samplerate_divider); | |
577 | arg[0] = devc->cur_samplerate_divider & 0xff; | |
578 | arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8; | |
579 | arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16; | |
580 | arg[3] = 0x00; | |
581 | if (write_longcommand(devc, CMD_SET_DIVIDER, arg) != SR_OK) | |
582 | return SR_ERR; | |
acc885c7 | 583 | |
4bd80e12 | 584 | /* Send extended sample limit and pre/post-trigger capture ratio. */ |
585 | arg[0] = ((readcount - 1) & 0xff); | |
586 | arg[1] = ((readcount - 1) & 0xff00) >> 8; | |
587 | arg[2] = ((readcount - 1) & 0xff0000) >> 16; | |
588 | arg[3] = ((readcount - 1) & 0xff000000) >> 24; | |
1e0de846 | 589 | if (write_longcommand(devc, CMD_CAPTURE_DELAY, arg) != SR_OK) |
4bd80e12 | 590 | return SR_ERR; |
591 | arg[0] = ((delaycount - 1) & 0xff); | |
592 | arg[1] = ((delaycount - 1) & 0xff00) >> 8; | |
593 | arg[2] = ((delaycount - 1) & 0xff0000) >> 16; | |
594 | arg[3] = ((delaycount - 1) & 0xff000000) >> 24; | |
1e0de846 | 595 | if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK) |
4bd80e12 | 596 | return SR_ERR; |
acc885c7 | 597 | |
4bd80e12 | 598 | /* Flag register. */ |
599 | sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s", | |
600 | devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off", | |
601 | devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off", | |
602 | devc->flag_reg & FLAG_RLE ? "on" : "off", | |
603 | devc->flag_reg & FLAG_FILTER ? "on": "off", | |
604 | devc->flag_reg & FLAG_DEMUX ? "on" : "off"); | |
605 | ||
b94cff40 | 606 | /* |
607 | * Enable/disable OLS channel groups in the flag register according | |
608 | * to the channel mask. 1 means "disable channel". | |
609 | */ | |
610 | devc->flag_reg &= ~0x3c; | |
acc885c7 | 611 | devc->flag_reg |= ~(pols_changrp_mask << 2) & 0x3c; |
b94cff40 | 612 | sr_dbg("flag_reg = %x", devc->flag_reg); |
613 | ||
614 | /* | |
176d785d UH |
615 | * In demux mode the OLS is processing two 8-bit or 16-bit samples |
616 | * in parallel and for this to work the lower two bits of the four | |
b94cff40 | 617 | * "channel_disable" bits must be replicated to the upper two bits. |
618 | */ | |
619 | flag_tmp = devc->flag_reg; | |
620 | if (devc->flag_reg & FLAG_DEMUX) { | |
621 | flag_tmp &= ~0x30; | |
acc885c7 | 622 | flag_tmp |= ~(pols_changrp_mask << 4) & 0x30; |
b94cff40 | 623 | } |
624 | arg[0] = flag_tmp & 0xff; | |
625 | arg[1] = flag_tmp >> 8; | |
4bd80e12 | 626 | arg[2] = arg[3] = 0x00; |
627 | if (write_longcommand(devc, CMD_SET_FLAGS, arg) != SR_OK) | |
628 | return SR_ERR; | |
629 | ||
630 | /* Start acquisition on the device. */ | |
631 | if (write_shortcommand(devc, CMD_RUN) != SR_OK) | |
632 | return SR_ERR; | |
633 | ||
634 | /* Reset all operational states. */ | |
635 | devc->rle_count = devc->num_transfers = 0; | |
636 | devc->num_samples = devc->num_bytes = 0; | |
637 | devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0; | |
638 | memset(devc->sample, 0, 4); | |
639 | ||
bee2b016 | 640 | std_session_send_df_header(sdi); |
4bd80e12 | 641 | |
642 | /* Hook up a dummy handler to receive data from the device. */ | |
c650d3ec | 643 | sr_session_source_add(sdi->session, -1, 0, 10, p_ols_receive_data, |
695dc859 | 644 | (struct sr_dev_inst *)sdi); |
4bd80e12 | 645 | |
646 | return SR_OK; | |
647 | } | |
648 | ||
695dc859 | 649 | static int dev_acquisition_stop(struct sr_dev_inst *sdi) |
4bd80e12 | 650 | { |
651 | struct dev_context *devc; | |
4bd80e12 | 652 | |
653 | devc = sdi->priv; | |
654 | ||
4bd80e12 | 655 | write_shortcommand(devc, CMD_RESET); |
656 | write_shortcommand(devc, CMD_RESET); | |
657 | write_shortcommand(devc, CMD_RESET); | |
658 | write_shortcommand(devc, CMD_RESET); | |
659 | write_shortcommand(devc, CMD_RESET); | |
660 | ||
dd7a4a71 | 661 | sr_session_source_remove(sdi->session, -1); |
4bd80e12 | 662 | |
bee2b016 | 663 | std_session_send_df_end(sdi); |
4bd80e12 | 664 | |
665 | return SR_OK; | |
666 | } | |
667 | ||
668 | SR_PRIV struct sr_dev_driver p_ols_driver_info = { | |
acc885c7 | 669 | .name = "p-ols", |
4bd80e12 | 670 | .longname = "Pipistrello OLS", |
671 | .api_version = 1, | |
c2fdcc25 | 672 | .init = std_init, |
700d6b64 | 673 | .cleanup = std_cleanup, |
4bd80e12 | 674 | .scan = scan, |
c01bf34c | 675 | .dev_list = std_dev_list, |
4bd80e12 | 676 | .dev_clear = dev_clear, |
677 | .config_get = config_get, | |
678 | .config_set = config_set, | |
679 | .config_list = config_list, | |
680 | .dev_open = dev_open, | |
681 | .dev_close = dev_close, | |
682 | .dev_acquisition_start = dev_acquisition_start, | |
683 | .dev_acquisition_stop = dev_acquisition_stop, | |
41812aca | 684 | .context = NULL, |
4bd80e12 | 685 | }; |
dd5c48a6 | 686 | SR_REGISTER_DEV_DRIVER(p_ols_driver_info); |