[libsigrok.git] / src / hardware / openbench-logic-sniffer / api.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include "protocol.h"

#define SERIALCOMM "115200/8n1"

static const uint32_t scanopts[] = {
	SR_CONF_CONN,
	SR_CONF_SERIALCOMM,
};

static const uint32_t drvopts[] = {
	SR_CONF_LOGIC_ANALYZER,
};

static const uint32_t devopts[] = {
	SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
	SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
	SR_CONF_EXTERNAL_CLOCK | SR_CONF_SET,
	SR_CONF_PATTERN_MODE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_SWAP | SR_CONF_SET,
	SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET,
};

static const int32_t trigger_matches[] = {
	SR_TRIGGER_ZERO,
	SR_TRIGGER_ONE,
};

#define STR_PATTERN_NONE     "None"
#define STR_PATTERN_EXTERNAL "External"
#define STR_PATTERN_INTERNAL "Internal"

/* Supported methods of test pattern outputs */
enum {
	/**
	 * Capture pins 31:16 (unbuffered wing) output a test pattern
	 * that can captured on pins 0:15.
	 */
	PATTERN_EXTERNAL,

	/** Route test pattern internally to capture buffer. */
	PATTERN_INTERNAL,
};

static const char *patterns[] = {
	STR_PATTERN_NONE,
	STR_PATTERN_EXTERNAL,
	STR_PATTERN_INTERNAL,
};

/* Channels are numbered 0-31 (on the PCB silkscreen). */
SR_PRIV const char *ols_channel_names[] = {
	"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12",
	"13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
	"24", "25", "26", "27", "28", "29", "30", "31",
};

/* Default supported samplerates, can be overridden by device metadata. */
static const uint64_t samplerates[] = {
	SR_HZ(10),
	SR_MHZ(200),
	SR_HZ(1),
};

#define RESPONSE_DELAY_US (10 * 1000)

static GSList *scan(struct sr_dev_driver *di, GSList *options)
{
	struct sr_config *src;
	struct sr_dev_inst *sdi;
	struct sr_serial_dev_inst *serial;
	GSList *l;
	int ret;
	unsigned int i;
	const char *conn, *serialcomm;
	char buf[8];

	conn = serialcomm = NULL;
	for (l = options; l; l = l->next) {
		src = l->data;
		switch (src->key) {
		case SR_CONF_CONN:
			conn = g_variant_get_string(src->data, NULL);
			break;
		case SR_CONF_SERIALCOMM:
			serialcomm = g_variant_get_string(src->data, NULL);
			break;
		}
	}
	if (!conn)
		return NULL;

	if (!serialcomm)
		serialcomm = SERIALCOMM;

	serial = sr_serial_dev_inst_new(conn, serialcomm);

	/* The discovery procedure is like this: first send the Reset
	 * command (0x00) 5 times, since the device could be anywhere
	 * in a 5-byte command. Then send the ID command (0x02).
	 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
	 * have a match.
	 */
	sr_info("Probing %s.", conn);
	if (serial_open(serial, SERIAL_RDWR) != SR_OK)
		return NULL;

	if (ols_send_reset(serial) != SR_OK) {
		serial_close(serial);
		sr_err("Could not use port %s. Quitting.", conn);
		return NULL;
	}
	send_shortcommand(serial, CMD_ID);

	g_usleep(RESPONSE_DELAY_US);

	if (sp_input_waiting(serial->data) == 0) {
		sr_dbg("Didn't get any reply.");
		return NULL;
	}

	ret = serial_read_blocking(serial, buf, 4, serial_timeout(serial, 4));
	if (ret != 4) {
		sr_err("Invalid reply (expected 4 bytes, got %d).", ret);
		return NULL;
	}

	if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4)) {
		sr_err("Invalid reply (expected '1SLO' or '1ALS', got "
		       "'%c%c%c%c').", buf[0], buf[1], buf[2], buf[3]);
		return NULL;
	}

	/* Definitely using the OLS protocol, check if it supports
	 * the metadata command.
	 */
	send_shortcommand(serial, CMD_METADATA);

	g_usleep(RESPONSE_DELAY_US);

	if (sp_input_waiting(serial->data) != 0) {
		/* Got metadata. */
		sdi = get_metadata(serial);
	} else {
		/* Not an OLS -- some other board that uses the sump protocol. */
		sr_info("Device does not support metadata.");
		sdi = g_malloc0(sizeof(struct sr_dev_inst));
		sdi->status = SR_ST_INACTIVE;
		sdi->vendor = g_strdup("Sump");
		sdi->model = g_strdup("Logic Analyzer");
		sdi->version = g_strdup("v1.0");
		for (i = 0; i < ARRAY_SIZE(ols_channel_names); i++)
			sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE,
					ols_channel_names[i]);
		sdi->priv = ols_dev_new();
	}
	/* Configure samplerate and divider. */
	if (ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
		sr_dbg("Failed to set default samplerate (%"PRIu64").",
				DEFAULT_SAMPLERATE);
	sdi->inst_type = SR_INST_SERIAL;
	sdi->conn = serial;

	serial_close(serial);

	return std_scan_complete(di, g_slist_append(NULL, sdi));
}

static int config_get(uint32_t key, GVariant **data,
	const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
	struct dev_context *devc;

	(void)cg;

	if (!sdi)
		return SR_ERR_ARG;

	devc = sdi->priv;
	switch (key) {
	case SR_CONF_SAMPLERATE:
		*data = g_variant_new_uint64(devc->cur_samplerate);
		break;
	case SR_CONF_CAPTURE_RATIO:
		*data = g_variant_new_uint64(devc->capture_ratio);
		break;
	case SR_CONF_LIMIT_SAMPLES:
		*data = g_variant_new_uint64(devc->limit_samples);
		break;
	case SR_CONF_PATTERN_MODE:
		if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE)
			*data = g_variant_new_string(STR_PATTERN_EXTERNAL);
		else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE)
			*data = g_variant_new_string(STR_PATTERN_INTERNAL);
		else
			*data = g_variant_new_string(STR_PATTERN_NONE);
		break;
	case SR_CONF_RLE:
		*data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE);
		break;
	default:
		return SR_ERR_NA;
	}

	return SR_OK;
}

static int config_set(uint32_t key, GVariant *data,
	const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
	struct dev_context *devc;
	uint16_t flag;
	uint64_t tmp_u64;
	int ret;
	const char *stropt;

	(void)cg;

	devc = sdi->priv;

	switch (key) {
	case SR_CONF_SAMPLERATE:
		tmp_u64 = g_variant_get_uint64(data);
		if (tmp_u64 < samplerates[0] || tmp_u64 > samplerates[1])
			return SR_ERR_SAMPLERATE;
		ret = ols_set_samplerate(sdi, g_variant_get_uint64(data));
		break;
	case SR_CONF_LIMIT_SAMPLES:
		tmp_u64 = g_variant_get_uint64(data);
		if (tmp_u64 < MIN_NUM_SAMPLES)
			return SR_ERR;
		devc->limit_samples = tmp_u64;
		ret = SR_OK;
		break;
	case SR_CONF_CAPTURE_RATIO:
		devc->capture_ratio = g_variant_get_uint64(data);
		if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
			ret = SR_ERR;
		else
			ret = SR_OK;
		break;
	case SR_CONF_EXTERNAL_CLOCK:
		if (g_variant_get_boolean(data)) {
			sr_info("Enabling external clock.");
			devc->flag_reg |= FLAG_CLOCK_EXTERNAL;
		} else {
			sr_info("Disabled external clock.");
			devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL;
		}
		ret = SR_OK;
		break;
	case SR_CONF_PATTERN_MODE:
		stropt = g_variant_get_string(data, NULL);
		ret = SR_OK;
		flag = 0xffff;
		if (!strcmp(stropt, STR_PATTERN_NONE)) {
			sr_info("Disabling test modes.");
			flag = 0x0000;
		}else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) {
			sr_info("Enabling internal test mode.");
			flag = FLAG_INTERNAL_TEST_MODE;
		} else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) {
			sr_info("Enabling external test mode.");
			flag = FLAG_EXTERNAL_TEST_MODE;
		} else {
			ret = SR_ERR;
		}
		if (flag != 0xffff) {
			devc->flag_reg &= ~(FLAG_INTERNAL_TEST_MODE | FLAG_EXTERNAL_TEST_MODE);
			devc->flag_reg |= flag;
		}
		break;
	case SR_CONF_SWAP:
		if (g_variant_get_boolean(data)) {
			sr_info("Enabling channel swapping.");
			devc->flag_reg |= FLAG_SWAP_CHANNELS;
		} else {
			sr_info("Disabling channel swapping.");
			devc->flag_reg &= ~FLAG_SWAP_CHANNELS;
		}
		ret = SR_OK;
		break;

	case SR_CONF_RLE:
		if (g_variant_get_boolean(data)) {
			sr_info("Enabling RLE.");
			devc->flag_reg |= FLAG_RLE;
		} else {
			sr_info("Disabling RLE.");
			devc->flag_reg &= ~FLAG_RLE;
		}
		ret = SR_OK;
		break;
	default:
		ret = SR_ERR_NA;
	}

	return ret;
}

static int config_list(uint32_t key, GVariant **data,
	const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
	struct dev_context *devc;
	GVariant *grange[2];
	int num_ols_changrp, i;

	switch (key) {
	case SR_CONF_SCAN_OPTIONS:
	case SR_CONF_DEVICE_OPTIONS:
		return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
	case SR_CONF_SAMPLERATE:
		*data = std_gvar_samplerates_steps(ARRAY_AND_SIZE(samplerates));
		break;
	case SR_CONF_TRIGGER_MATCH:
		*data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
		break;
	case SR_CONF_PATTERN_MODE:
		*data = g_variant_new_strv(ARRAY_AND_SIZE(patterns));
		break;
	case SR_CONF_LIMIT_SAMPLES:
		if (!sdi)
			return SR_ERR_ARG;
		devc = sdi->priv;
		if (devc->flag_reg & FLAG_RLE)
			return SR_ERR_NA;
		if (devc->max_samples == 0)
			/* Device didn't specify sample memory size in metadata. */
			return SR_ERR_NA;
		/*
		 * Channel groups are turned off if no channels in that group are
		 * enabled, making more room for samples for the enabled group.
		*/
		ols_channel_mask(sdi);
		num_ols_changrp = 0;
		for (i = 0; i < 4; i++) {
			if (devc->channel_mask & (0xff << (i * 8)))
				num_ols_changrp++;
		}
		grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES);
		if (num_ols_changrp)
			grange[1] = g_variant_new_uint64(devc->max_samples / num_ols_changrp);
		else
			grange[1] = g_variant_new_uint64(MIN_NUM_SAMPLES);
		*data = g_variant_new_tuple(grange, 2);
		break;
	default:
		return SR_ERR_NA;
	}

	return SR_OK;
}

static int set_trigger(const struct sr_dev_inst *sdi, int stage)
{
	struct dev_context *devc;
	struct sr_serial_dev_inst *serial;
	uint8_t cmd, arg[4];

	devc = sdi->priv;
	serial = sdi->conn;

	cmd = CMD_SET_TRIGGER_MASK + stage * 4;
	arg[0] = devc->trigger_mask[stage] & 0xff;
	arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff;
	arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff;
	arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff;
	if (send_longcommand(serial, cmd, arg) != SR_OK)
		return SR_ERR;

	cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
	arg[0] = devc->trigger_value[stage] & 0xff;
	arg[1] = (devc->trigger_value[stage] >> 8) & 0xff;
	arg[2] = (devc->trigger_value[stage] >> 16) & 0xff;
	arg[3] = (devc->trigger_value[stage] >> 24) & 0xff;
	if (send_longcommand(serial, cmd, arg) != SR_OK)
		return SR_ERR;

	cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
	arg[0] = arg[1] = arg[3] = 0x00;
	arg[2] = stage;
	if (stage == devc->num_stages)
		/* Last stage, fire when this one matches. */
		arg[3] |= TRIGGER_START;
	if (send_longcommand(serial, cmd, arg) != SR_OK)
		return SR_ERR;

	return SR_OK;
}

static int dev_acquisition_start(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_serial_dev_inst *serial;
	uint16_t samplecount, readcount, delaycount;
	uint8_t ols_changrp_mask, arg[4];
	int num_ols_changrp;
	int ret, i;

	devc = sdi->priv;
	serial = sdi->conn;

	ols_channel_mask(sdi);

	num_ols_changrp = 0;
	ols_changrp_mask = 0;
	for (i = 0; i < 4; i++) {
		if (devc->channel_mask & (0xff << (i * 8))) {
			ols_changrp_mask |= (1 << i);
			num_ols_changrp++;
		}
	}

	/*
	 * Limit readcount to prevent reading past the end of the hardware
	 * buffer.
	 */
	samplecount = MIN(devc->max_samples / num_ols_changrp, devc->limit_samples);
	readcount = samplecount / 4;

	/* Rather read too many samples than too few. */
	if (samplecount % 4 != 0)
		readcount++;

	/* Basic triggers. */
	if (ols_convert_trigger(sdi) != SR_OK) {
		sr_err("Failed to configure channels.");
		return SR_ERR;
	}
	if (devc->num_stages > 0) {
		/*
		 * According to http://mygizmos.org/ols/Logic-Sniffer-FPGA-Spec.pdf
		 * reset command must be send prior each arm command
		 */
		sr_dbg("Send reset command before trigger configure");
		if (ols_send_reset(serial) != SR_OK)
			return SR_ERR;

		delaycount = readcount * (1 - devc->capture_ratio / 100.0);
		devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
		for (i = 0; i <= devc->num_stages; i++) {
			sr_dbg("Setting OLS stage %d trigger.", i);
			if ((ret = set_trigger(sdi, i)) != SR_OK)
				return ret;
		}
	} else {
		/* No triggers configured, force trigger on first stage. */
		sr_dbg("Forcing trigger at stage 0.");
		if ((ret = set_trigger(sdi, 0)) != SR_OK)
			return ret;
		delaycount = readcount;
	}

	/* Samplerate. */
	sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
			devc->cur_samplerate, devc->cur_samplerate_divider);
	arg[0] = devc->cur_samplerate_divider & 0xff;
	arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8;
	arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16;
	arg[3] = 0x00;
	if (send_longcommand(serial, CMD_SET_DIVIDER, arg) != SR_OK)
		return SR_ERR;

	/* Send sample limit and pre/post-trigger capture ratio. */
	sr_dbg("Setting sample limit %d, trigger point at %d",
			(readcount - 1) * 4, (delaycount - 1) * 4);
	arg[0] = ((readcount - 1) & 0xff);
	arg[1] = ((readcount - 1) & 0xff00) >> 8;
	arg[2] = ((delaycount - 1) & 0xff);
	arg[3] = ((delaycount - 1) & 0xff00) >> 8;
	if (send_longcommand(serial, CMD_CAPTURE_SIZE, arg) != SR_OK)
		return SR_ERR;

	/* Flag register. */
	sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
			devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
			devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off",
			devc->flag_reg & FLAG_RLE ? "on" : "off",
			devc->flag_reg & FLAG_FILTER ? "on": "off",
			devc->flag_reg & FLAG_DEMUX ? "on" : "off");
	/*
	 * Enable/disable OLS channel groups in the flag register according
	 * to the channel mask. 1 means "disable channel".
	 */
	devc->flag_reg |= ~(ols_changrp_mask << 2) & 0x3c;
	arg[0] = devc->flag_reg & 0xff;
	arg[1] = devc->flag_reg >> 8;
	arg[2] = arg[3] = 0x00;
	if (send_longcommand(serial, CMD_SET_FLAGS, arg) != SR_OK)
		return SR_ERR;

	/* Start acquisition on the device. */
	if (send_shortcommand(serial, CMD_RUN) != SR_OK)
		return SR_ERR;

	/* Reset all operational states. */
	devc->rle_count = devc->num_transfers = 0;
	devc->num_samples = devc->num_bytes = 0;
	devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0;
	memset(devc->sample, 0, 4);

	std_session_send_df_header(sdi);

	/* If the device stops sending for longer than it takes to send a byte,
	 * that means it's finished. But wait at least 100 ms to be safe.
	 */
	serial_source_add(sdi->session, serial, G_IO_IN, 100,
			ols_receive_data, (struct sr_dev_inst *)sdi);

	return SR_OK;
}

static int dev_acquisition_stop(struct sr_dev_inst *sdi)
{
	abort_acquisition(sdi);

	return SR_OK;
}

static struct sr_dev_driver ols_driver_info = {
	.name = "ols",
	.longname = "Openbench Logic Sniffer",
	.api_version = 1,
	.init = std_init,
	.cleanup = std_cleanup,
	.scan = scan,
	.dev_list = std_dev_list,
	.dev_clear = std_dev_clear,
	.config_get = config_get,
	.config_set = config_set,
	.config_list = config_list,
	.dev_open = std_serial_dev_open,
	.dev_close = std_serial_dev_close,
	.dev_acquisition_start = dev_acquisition_start,
	.dev_acquisition_stop = dev_acquisition_stop,
	.context = NULL,
};
SR_REGISTER_DEV_DRIVER(ols_driver_info);
Commit	Line	Data
0aba65da	1	/*
50985c20	2	* This file is part of the libsigrok project.
0aba65da	3	*
13d8e03c	4	* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
0aba65da UH	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation, either version 3 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
6ec6c43b	20	#include <config.h>
515ab088	21	#include "protocol.h"
0aba65da UH	22
	23	#define SERIALCOMM "115200/8n1"
	24
a0e0bb41	25	static const uint32_t scanopts[] = {
1953564a BV	26	SR_CONF_CONN,
1953564a BV	27	SR_CONF_SERIALCOMM,
aeabd308 UH	28	};
aeabd308 UH	29
55fb76b3 UH	30	static const uint32_t drvopts[] = {
	31	SR_CONF_LOGIC_ANALYZER,
	32	};
	33
f254bc4b	34	static const uint32_t devopts[] = {
5827f61b BV	35	SR_CONF_LIMIT_SAMPLES \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	36	SR_CONF_SAMPLERATE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	37	SR_CONF_TRIGGER_MATCH \| SR_CONF_LIST,
	38	SR_CONF_CAPTURE_RATIO \| SR_CONF_GET \| SR_CONF_SET,
	39	SR_CONF_EXTERNAL_CLOCK \| SR_CONF_SET,
	40	SR_CONF_PATTERN_MODE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	41	SR_CONF_SWAP \| SR_CONF_SET,
	42	SR_CONF_RLE \| SR_CONF_GET \| SR_CONF_SET,
0aba65da UH	43	};
0aba65da UH	44
91fd0f72 BV	45	static const int32_t trigger_matches[] = {
	46	SR_TRIGGER_ZERO,
	47	SR_TRIGGER_ONE,
	48	};
	49
6d16fdfb BV	50	#define STR_PATTERN_NONE "None"
	51	#define STR_PATTERN_EXTERNAL "External"
	52	#define STR_PATTERN_INTERNAL "Internal"
967760a8 MR	53
	54	/* Supported methods of test pattern outputs */
	55	enum {
	56	/**
	57	* Capture pins 31:16 (unbuffered wing) output a test pattern
	58	* that can captured on pins 0:15.
	59	*/
	60	PATTERN_EXTERNAL,
	61
	62	/** Route test pattern internally to capture buffer. */
	63	PATTERN_INTERNAL,
	64	};
	65
7c07a178	66	static const char *patterns[] = {
6d16fdfb	67	STR_PATTERN_NONE,
7c07a178 UH	68	STR_PATTERN_EXTERNAL,
	69	STR_PATTERN_INTERNAL,
	70	};
	71
ba7dd8bb	72	/* Channels are numbered 0-31 (on the PCB silkscreen). */
53cda65a	73	SR_PRIV const char *ols_channel_names[] = {
78693401 UH	74	"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12",
	75	"13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
	76	"24", "25", "26", "27", "28", "29", "30", "31",
0aba65da UH	77	};
0aba65da UH	78
d3b38ad3	79	/* Default supported samplerates, can be overridden by device metadata. */
e46aa4f6 BV	80	static const uint64_t samplerates[] = {
	81	SR_HZ(10),
	82	SR_MHZ(200),
	83	SR_HZ(1),
0aba65da UH	84	};
0aba65da UH	85
1a46cc62 UH	86	#define RESPONSE_DELAY_US (10 * 1000)
1a46cc62 UH	87
4f840ce9	88	static GSList scan(struct sr_dev_driver di, GSList *options)
0aba65da	89	{
1987b8d6	90	struct sr_config *src;
0aba65da	91	struct sr_dev_inst *sdi;
0aba65da	92	struct sr_serial_dev_inst *serial;
43376f33	93	GSList *l;
07ffa5b3 UH	94	int ret;
07ffa5b3 UH	95	unsigned int i;
0aba65da UH	96	const char conn, serialcomm;
	97	char buf[8];
	98
0aba65da UH	99	conn = serialcomm = NULL;
0aba65da UH	100	for (l = options; l; l = l->next) {
1987b8d6 BV	101	src = l->data;
1987b8d6 BV	102	switch (src->key) {
1953564a	103	case SR_CONF_CONN:
e46aa4f6	104	conn = g_variant_get_string(src->data, NULL);
0aba65da	105	break;
1953564a	106	case SR_CONF_SERIALCOMM:
e46aa4f6	107	serialcomm = g_variant_get_string(src->data, NULL);
0aba65da UH	108	break;
	109	}
	110	}
	111	if (!conn)
	112	return NULL;
	113
98fec29e	114	if (!serialcomm)
0aba65da UH	115	serialcomm = SERIALCOMM;
0aba65da UH	116
91219afc	117	serial = sr_serial_dev_inst_new(conn, serialcomm);
0aba65da UH	118
	119	/* The discovery procedure is like this: first send the Reset
	120	* command (0x00) 5 times, since the device could be anywhere
	121	* in a 5-byte command. Then send the ID command (0x02).
	122	* If the device responds with 4 bytes ("OLS1" or "SLA1"), we
	123	* have a match.
	124	*/
	125	sr_info("Probing %s.", conn);
4ded59ee	126	if (serial_open(serial, SERIAL_RDWR) != SR_OK)
0aba65da UH	127	return NULL;
0aba65da UH	128
244995a2	129	if (ols_send_reset(serial) != SR_OK) {
0aba65da UH	130	serial_close(serial);
	131	sr_err("Could not use port %s. Quitting.", conn);
	132	return NULL;
	133	}
	134	send_shortcommand(serial, CMD_ID);
	135
1a46cc62	136	g_usleep(RESPONSE_DELAY_US);
0aba65da	137
ed936ccc UH	138	if (sp_input_waiting(serial->data) == 0) {
ed936ccc UH	139	sr_dbg("Didn't get any reply.");
0aba65da	140	return NULL;
ed936ccc UH	141	}
	142
	143	ret = serial_read_blocking(serial, buf, 4, serial_timeout(serial, 4));
	144	if (ret != 4) {
	145	sr_err("Invalid reply (expected 4 bytes, got %d).", ret);
0aba65da	146	return NULL;
ed936ccc UH	147	}
	148
	149	if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4)) {
	150	sr_err("Invalid reply (expected '1SLO' or '1ALS', got "
	151	"'%c%c%c%c').", buf[0], buf[1], buf[2], buf[3]);
0aba65da	152	return NULL;
ed936ccc	153	}
0aba65da UH	154
	155	/* Definitely using the OLS protocol, check if it supports
	156	* the metadata command.
	157	*/
	158	send_shortcommand(serial, CMD_METADATA);
ed936ccc	159
1a46cc62	160	g_usleep(RESPONSE_DELAY_US);
ed936ccc UH	161
ed936ccc UH	162	if (sp_input_waiting(serial->data) != 0) {
0aba65da UH	163	/* Got metadata. */
0aba65da UH	164	sdi = get_metadata(serial);
0aba65da UH	165	} else {
0aba65da UH	166	/* Not an OLS -- some other board that uses the sump protocol. */
72cd99b8	167	sr_info("Device does not support metadata.");
aac29cc1	168	sdi = g_malloc0(sizeof(struct sr_dev_inst));
0af636be UH	169	sdi->status = SR_ST_INACTIVE;
	170	sdi->vendor = g_strdup("Sump");
	171	sdi->model = g_strdup("Logic Analyzer");
	172	sdi->version = g_strdup("v1.0");
07ffa5b3	173	for (i = 0; i < ARRAY_SIZE(ols_channel_names); i++)
5e23fcab	174	sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE,
c368e6f3	175	ols_channel_names[i]);
e57057ae	176	sdi->priv = ols_dev_new();
0aba65da	177	}
bf256783 BV	178	/* Configure samplerate and divider. */
	179	if (ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
	180	sr_dbg("Failed to set default samplerate (%"PRIu64").",
	181	DEFAULT_SAMPLERATE);
459a0f26 BV	182	sdi->inst_type = SR_INST_SERIAL;
459a0f26 BV	183	sdi->conn = serial;
bf256783	184
0aba65da UH	185	serial_close(serial);
0aba65da UH	186
43376f33	187	return std_scan_complete(di, g_slist_append(NULL, sdi));
0aba65da UH	188	}
0aba65da UH	189
dd7a72ea UH	190	static int config_get(uint32_t key, GVariant **data,
dd7a72ea UH	191	const struct sr_dev_inst sdi, const struct sr_channel_group cg)
0aba65da UH	192	{
	193	struct dev_context *devc;
	194
53b4680f	195	(void)cg;
8f996b89	196
0c05591a BV	197	if (!sdi)
	198	return SR_ERR_ARG;
	199
	200	devc = sdi->priv;
584560f1	201	switch (key) {
123e1313	202	case SR_CONF_SAMPLERATE:
0c05591a BV	203	*data = g_variant_new_uint64(devc->cur_samplerate);
	204	break;
	205	case SR_CONF_CAPTURE_RATIO:
	206	*data = g_variant_new_uint64(devc->capture_ratio);
	207	break;
	208	case SR_CONF_LIMIT_SAMPLES:
	209	*data = g_variant_new_uint64(devc->limit_samples);
	210	break;
967760a8 MR	211	case SR_CONF_PATTERN_MODE:
	212	if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE)
	213	*data = g_variant_new_string(STR_PATTERN_EXTERNAL);
	214	else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE)
	215	*data = g_variant_new_string(STR_PATTERN_INTERNAL);
6d16fdfb BV	216	else
6d16fdfb BV	217	*data = g_variant_new_string(STR_PATTERN_NONE);
967760a8	218	break;
0c05591a BV	219	case SR_CONF_RLE:
0c05591a BV	220	*data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE);
7730e4f0	221	break;
0aba65da	222	default:
bd6fbf62	223	return SR_ERR_NA;
0aba65da UH	224	}
	225
	226	return SR_OK;
	227	}
	228
dd7a72ea UH	229	static int config_set(uint32_t key, GVariant *data,
dd7a72ea UH	230	const struct sr_dev_inst sdi, const struct sr_channel_group cg)
0aba65da UH	231	{
0aba65da UH	232	struct dev_context *devc;
6d16fdfb	233	uint16_t flag;
e46aa4f6	234	uint64_t tmp_u64;
6d16fdfb	235	int ret;
967760a8	236	const char *stropt;
0aba65da	237
53b4680f	238	(void)cg;
8f996b89	239
0aba65da UH	240	devc = sdi->priv;
0aba65da UH	241
584560f1	242	switch (key) {
1953564a	243	case SR_CONF_SAMPLERATE:
e46aa4f6 BV	244	tmp_u64 = g_variant_get_uint64(data);
	245	if (tmp_u64 < samplerates[0] \|\| tmp_u64 > samplerates[1])
	246	return SR_ERR_SAMPLERATE;
	247	ret = ols_set_samplerate(sdi, g_variant_get_uint64(data));
0aba65da	248	break;
1953564a	249	case SR_CONF_LIMIT_SAMPLES:
e46aa4f6 BV	250	tmp_u64 = g_variant_get_uint64(data);
e46aa4f6 BV	251	if (tmp_u64 < MIN_NUM_SAMPLES)
0aba65da	252	return SR_ERR;
e46aa4f6	253	devc->limit_samples = tmp_u64;
0aba65da UH	254	ret = SR_OK;
0aba65da UH	255	break;
1953564a	256	case SR_CONF_CAPTURE_RATIO:
e46aa4f6	257	devc->capture_ratio = g_variant_get_uint64(data);
a5c38703	258	if (devc->capture_ratio < 0 \|\| devc->capture_ratio > 100)
0aba65da	259	ret = SR_ERR;
a5c38703	260	else
0aba65da UH	261	ret = SR_OK;
0aba65da UH	262	break;
eb1b610b MR	263	case SR_CONF_EXTERNAL_CLOCK:
	264	if (g_variant_get_boolean(data)) {
	265	sr_info("Enabling external clock.");
	266	devc->flag_reg \|= FLAG_CLOCK_EXTERNAL;
	267	} else {
	268	sr_info("Disabled external clock.");
	269	devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL;
	270	}
	271	ret = SR_OK;
	272	break;
967760a8 MR	273	case SR_CONF_PATTERN_MODE:
	274	stropt = g_variant_get_string(data, NULL);
	275	ret = SR_OK;
6d16fdfb BV	276	flag = 0xffff;
	277	if (!strcmp(stropt, STR_PATTERN_NONE)) {
	278	sr_info("Disabling test modes.");
	279	flag = 0x0000;
	280	}else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) {
967760a8	281	sr_info("Enabling internal test mode.");
6d16fdfb	282	flag = FLAG_INTERNAL_TEST_MODE;
967760a8 MR	283	} else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) {
967760a8 MR	284	sr_info("Enabling external test mode.");
6d16fdfb	285	flag = FLAG_EXTERNAL_TEST_MODE;
967760a8 MR	286	} else {
	287	ret = SR_ERR;
	288	}
6d16fdfb BV	289	if (flag != 0xffff) {
	290	devc->flag_reg &= ~(FLAG_INTERNAL_TEST_MODE \| FLAG_EXTERNAL_TEST_MODE);
	291	devc->flag_reg \|= flag;
	292	}
967760a8	293	break;
7b0a57fd MR	294	case SR_CONF_SWAP:
	295	if (g_variant_get_boolean(data)) {
	296	sr_info("Enabling channel swapping.");
3f239f08	297	devc->flag_reg \|= FLAG_SWAP_CHANNELS;
7b0a57fd MR	298	} else {
7b0a57fd MR	299	sr_info("Disabling channel swapping.");
3f239f08	300	devc->flag_reg &= ~FLAG_SWAP_CHANNELS;
7b0a57fd MR	301	}
	302	ret = SR_OK;
	303	break;
	304
1953564a	305	case SR_CONF_RLE:
e46aa4f6	306	if (g_variant_get_boolean(data)) {
0aba65da UH	307	sr_info("Enabling RLE.");
0aba65da UH	308	devc->flag_reg \|= FLAG_RLE;
aeea0572 BV	309	} else {
	310	sr_info("Disabling RLE.");
	311	devc->flag_reg &= ~FLAG_RLE;
0aba65da UH	312	}
	313	ret = SR_OK;
	314	break;
	315	default:
bd6fbf62	316	ret = SR_ERR_NA;
0aba65da UH	317	}
	318
	319	return ret;
	320	}
	321
dd7a72ea UH	322	static int config_list(uint32_t key, GVariant **data,
dd7a72ea UH	323	const struct sr_dev_inst sdi, const struct sr_channel_group cg)
a1c743fc	324	{
f0de2dd0	325	struct dev_context *devc;
463160cb	326	GVariant *grange[2];
91fd0f72	327	int num_ols_changrp, i;
a1c743fc	328
a1c743fc	329	switch (key) {
0d485e30	330	case SR_CONF_SCAN_OPTIONS:
9a6517d1	331	case SR_CONF_DEVICE_OPTIONS:
e66d1892	332	return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
a1c743fc	333	case SR_CONF_SAMPLERATE:
53012da6	334	*data = std_gvar_samplerates_steps(ARRAY_AND_SIZE(samplerates));
a1c743fc	335	break;
91fd0f72	336	case SR_CONF_TRIGGER_MATCH:
53012da6	337	*data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
c50277a6	338	break;
7c07a178	339	case SR_CONF_PATTERN_MODE:
53012da6	340	*data = g_variant_new_strv(ARRAY_AND_SIZE(patterns));
7c07a178	341	break;
f0de2dd0 BV	342	case SR_CONF_LIMIT_SAMPLES:
	343	if (!sdi)
	344	return SR_ERR_ARG;
	345	devc = sdi->priv;
	346	if (devc->flag_reg & FLAG_RLE)
	347	return SR_ERR_NA;
	348	if (devc->max_samples == 0)
	349	/* Device didn't specify sample memory size in metadata. */
	350	return SR_ERR_NA;
	351	/*
ba7dd8bb	352	* Channel groups are turned off if no channels in that group are
f0de2dd0 BV	353	* enabled, making more room for samples for the enabled group.
f0de2dd0 BV	354	*/
91fd0f72 BV	355	ols_channel_mask(sdi);
91fd0f72 BV	356	num_ols_changrp = 0;
f0de2dd0	357	for (i = 0; i < 4; i++) {
ba7dd8bb	358	if (devc->channel_mask & (0xff << (i * 8)))
91fd0f72	359	num_ols_changrp++;
1e1dac0c	360	}
f0de2dd0	361	grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES);
91fd0f72 BV	362	if (num_ols_changrp)
	363	grange[1] = g_variant_new_uint64(devc->max_samples / num_ols_changrp);
	364	else
	365	grange[1] = g_variant_new_uint64(MIN_NUM_SAMPLES);
f0de2dd0 BV	366	*data = g_variant_new_tuple(grange, 2);
f0de2dd0 BV	367	break;
a1c743fc	368	default:
bd6fbf62	369	return SR_ERR_NA;
a1c743fc BV	370	}
	371
	372	return SR_OK;
	373	}
	374
016e72f3 BV	375	static int set_trigger(const struct sr_dev_inst *sdi, int stage)
	376	{
	377	struct dev_context *devc;
	378	struct sr_serial_dev_inst *serial;
	379	uint8_t cmd, arg[4];
	380
	381	devc = sdi->priv;
	382	serial = sdi->conn;
	383
	384	cmd = CMD_SET_TRIGGER_MASK + stage * 4;
	385	arg[0] = devc->trigger_mask[stage] & 0xff;
	386	arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff;
	387	arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff;
	388	arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff;
	389	if (send_longcommand(serial, cmd, arg) != SR_OK)
	390	return SR_ERR;
	391
	392	cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
	393	arg[0] = devc->trigger_value[stage] & 0xff;
	394	arg[1] = (devc->trigger_value[stage] >> 8) & 0xff;
	395	arg[2] = (devc->trigger_value[stage] >> 16) & 0xff;
	396	arg[3] = (devc->trigger_value[stage] >> 24) & 0xff;
	397	if (send_longcommand(serial, cmd, arg) != SR_OK)
	398	return SR_ERR;
	399
	400	cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
	401	arg[0] = arg[1] = arg[3] = 0x00;
	402	arg[2] = stage;
	403	if (stage == devc->num_stages)
	404	/* Last stage, fire when this one matches. */
	405	arg[3] \|= TRIGGER_START;
	406	if (send_longcommand(serial, cmd, arg) != SR_OK)
	407	return SR_ERR;
	408
	409	return SR_OK;
	410	}
	411
695dc859	412	static int dev_acquisition_start(const struct sr_dev_inst *sdi)
0aba65da	413	{
0aba65da	414	struct dev_context *devc;
459a0f26	415	struct sr_serial_dev_inst *serial;
32f09bfd	416	uint16_t samplecount, readcount, delaycount;
91fd0f72 BV	417	uint8_t ols_changrp_mask, arg[4];
91fd0f72 BV	418	int num_ols_changrp;
016e72f3	419	int ret, i;
0aba65da UH	420
0aba65da UH	421	devc = sdi->priv;
459a0f26	422	serial = sdi->conn;
0aba65da	423
91fd0f72	424	ols_channel_mask(sdi);
0aba65da	425
91fd0f72 BV	426	num_ols_changrp = 0;
91fd0f72 BV	427	ols_changrp_mask = 0;
0aba65da	428	for (i = 0; i < 4; i++) {
ba7dd8bb	429	if (devc->channel_mask & (0xff << (i * 8))) {
91fd0f72 BV	430	ols_changrp_mask \|= (1 << i);
91fd0f72 BV	431	num_ols_changrp++;
0aba65da UH	432	}
	433	}
	434
	435	/*
	436	* Limit readcount to prevent reading past the end of the hardware
	437	* buffer.
	438	*/
91fd0f72	439	samplecount = MIN(devc->max_samples / num_ols_changrp, devc->limit_samples);
32f09bfd	440	readcount = samplecount / 4;
016e72f3 BV	441
	442	/* Rather read too many samples than too few. */
	443	if (samplecount % 4 != 0)
32f09bfd	444	readcount++;
0aba65da	445
016e72f3	446	/* Basic triggers. */
91fd0f72 BV	447	if (ols_convert_trigger(sdi) != SR_OK) {
	448	sr_err("Failed to configure channels.");
	449	return SR_ERR;
	450	}
	451	if (devc->num_stages > 0) {
b853eb76 GGM	452	/*
	453	* According to http://mygizmos.org/ols/Logic-Sniffer-FPGA-Spec.pdf
	454	* reset command must be send prior each arm command
	455	*/
	456	sr_dbg("Send reset command before trigger configure");
	457	if (ols_send_reset(serial) != SR_OK)
	458	return SR_ERR;
	459
0aba65da UH	460	delaycount = readcount * (1 - devc->capture_ratio / 100.0);
0aba65da UH	461	devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
016e72f3	462	for (i = 0; i <= devc->num_stages; i++) {
91fd0f72	463	sr_dbg("Setting OLS stage %d trigger.", i);
016e72f3 BV	464	if ((ret = set_trigger(sdi, i)) != SR_OK)
	465	return ret;
	466	}
0aba65da	467	} else {
016e72f3 BV	468	/* No triggers configured, force trigger on first stage. */
	469	sr_dbg("Forcing trigger at stage 0.");
	470	if ((ret = set_trigger(sdi, 0)) != SR_OK)
	471	return ret;
0aba65da UH	472	delaycount = readcount;
	473	}
	474
6d16fdfb	475	/* Samplerate. */
016e72f3	476	sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
6d16fdfb	477	devc->cur_samplerate, devc->cur_samplerate_divider);
016e72f3 BV	478	arg[0] = devc->cur_samplerate_divider & 0xff;
	479	arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8;
	480	arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16;
	481	arg[3] = 0x00;
	482	if (send_longcommand(serial, CMD_SET_DIVIDER, arg) != SR_OK)
0aba65da UH	483	return SR_ERR;
	484
	485	/* Send sample limit and pre/post-trigger capture ratio. */
016e72f3	486	sr_dbg("Setting sample limit %d, trigger point at %d",
6d16fdfb	487	(readcount - 1) * 4, (delaycount - 1) * 4);
016e72f3 BV	488	arg[0] = ((readcount - 1) & 0xff);
	489	arg[1] = ((readcount - 1) & 0xff00) >> 8;
	490	arg[2] = ((delaycount - 1) & 0xff);
	491	arg[3] = ((delaycount - 1) & 0xff00) >> 8;
	492	if (send_longcommand(serial, CMD_CAPTURE_SIZE, arg) != SR_OK)
0aba65da UH	493	return SR_ERR;
0aba65da UH	494
6d16fdfb	495	/* Flag register. */
625763e2 BV	496	sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
625763e2 BV	497	devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
6d16fdfb	498	devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off",
625763e2 BV	499	devc->flag_reg & FLAG_RLE ? "on" : "off",
	500	devc->flag_reg & FLAG_FILTER ? "on": "off",
	501	devc->flag_reg & FLAG_DEMUX ? "on" : "off");
91fd0f72 BV	502	/*
	503	* Enable/disable OLS channel groups in the flag register according
	504	* to the channel mask. 1 means "disable channel".
	505	*/
	506	devc->flag_reg \|= ~(ols_changrp_mask << 2) & 0x3c;
016e72f3 BV	507	arg[0] = devc->flag_reg & 0xff;
	508	arg[1] = devc->flag_reg >> 8;
	509	arg[2] = arg[3] = 0x00;
	510	if (send_longcommand(serial, CMD_SET_FLAGS, arg) != SR_OK)
0aba65da UH	511	return SR_ERR;
	512
	513	/* Start acquisition on the device. */
459a0f26	514	if (send_shortcommand(serial, CMD_RUN) != SR_OK)
0aba65da UH	515	return SR_ERR;
0aba65da UH	516
bf256783	517	/* Reset all operational states. */
6d16fdfb BV	518	devc->rle_count = devc->num_transfers = 0;
6d16fdfb BV	519	devc->num_samples = devc->num_bytes = 0;
625763e2	520	devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0;
abb39e6b	521	memset(devc->sample, 0, 4);
bf256783	522
bee2b016	523	std_session_send_df_header(sdi);
4afdfd46	524
8105e829 DE	525	/* If the device stops sending for longer than it takes to send a byte,
	526	* that means it's finished. But wait at least 100 ms to be safe.
	527	*/
	528	serial_source_add(sdi->session, serial, G_IO_IN, 100,
695dc859	529	ols_receive_data, (struct sr_dev_inst *)sdi);
0aba65da	530
0aba65da UH	531	return SR_OK;
	532	}
	533
695dc859	534	static int dev_acquisition_stop(struct sr_dev_inst *sdi)
0aba65da	535	{
0aba65da UH	536	abort_acquisition(sdi);
	537
	538	return SR_OK;
	539	}
	540
15a5bfe4	541	static struct sr_dev_driver ols_driver_info = {
0aba65da UH	542	.name = "ols",
	543	.longname = "Openbench Logic Sniffer",
	544	.api_version = 1,
c2fdcc25	545	.init = std_init,
700d6b64	546	.cleanup = std_cleanup,
03f4de8c	547	.scan = scan,
c01bf34c	548	.dev_list = std_dev_list,
f778bf02	549	.dev_clear = std_dev_clear,
035a1078 BV	550	.config_get = config_get,
035a1078 BV	551	.config_set = config_set,
a1c743fc	552	.config_list = config_list,
854434de	553	.dev_open = std_serial_dev_open,
bf2c987f	554	.dev_close = std_serial_dev_close,
03f4de8c BV	555	.dev_acquisition_start = dev_acquisition_start,
03f4de8c BV	556	.dev_acquisition_stop = dev_acquisition_stop,
41812aca	557	.context = NULL,
0aba65da	558	};
dd5c48a6	559	SR_REGISTER_DEV_DRIVER(ols_driver_info);