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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
911f1834 UH |
4 | * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>, |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
da0918aa | 23 | * ASIX SIGMA Logic Analyzer Driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
30 | #include <zlib.h> | |
b7f09cf8 UH |
31 | #include "sigrok.h" |
32 | #include "sigrok-internal.h" | |
28a35d8a HE |
33 | #include "asix-sigma.h" |
34 | ||
35 | #define USB_VENDOR 0xa600 | |
36 | #define USB_PRODUCT 0xa000 | |
37 | #define USB_DESCRIPTION "ASIX SIGMA" | |
38 | #define USB_VENDOR_NAME "ASIX" | |
39 | #define USB_MODEL_NAME "SIGMA" | |
40 | #define USB_MODEL_VERSION "" | |
ee492173 | 41 | #define TRIGGER_TYPES "rf10" |
464d12c7 | 42 | #define NUM_PROBES 16 |
28a35d8a | 43 | |
d68e2d1a | 44 | static GSList *dev_insts = NULL; |
28a35d8a | 45 | |
28a35d8a | 46 | static uint64_t supported_samplerates[] = { |
59df0c77 UH |
47 | SR_KHZ(200), |
48 | SR_KHZ(250), | |
49 | SR_KHZ(500), | |
50 | SR_MHZ(1), | |
51 | SR_MHZ(5), | |
52 | SR_MHZ(10), | |
53 | SR_MHZ(25), | |
54 | SR_MHZ(50), | |
55 | SR_MHZ(100), | |
56 | SR_MHZ(200), | |
28a35d8a HE |
57 | 0, |
58 | }; | |
59 | ||
d261dbbf UH |
60 | /* |
61 | * Probe numbers seem to go from 1-16, according to this image: | |
62 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
63 | * (the cable has two additional GND pins, and a TI and TO pin) | |
64 | */ | |
c37d2b1b | 65 | static const char *probe_names[NUM_PROBES + 1] = { |
464d12c7 KS |
66 | "1", |
67 | "2", | |
68 | "3", | |
69 | "4", | |
70 | "5", | |
71 | "6", | |
72 | "7", | |
73 | "8", | |
74 | "9", | |
75 | "10", | |
76 | "11", | |
77 | "12", | |
78 | "13", | |
79 | "14", | |
80 | "15", | |
d261dbbf | 81 | "16", |
464d12c7 KS |
82 | NULL, |
83 | }; | |
84 | ||
60679b18 | 85 | static struct sr_samplerates samplerates = { |
59df0c77 UH |
86 | SR_KHZ(200), |
87 | SR_MHZ(200), | |
c9140419 | 88 | SR_HZ(0), |
28a35d8a HE |
89 | supported_samplerates, |
90 | }; | |
91 | ||
ffedd0bf | 92 | static int hwcaps[] = { |
5a2326a7 UH |
93 | SR_HWCAP_LOGIC_ANALYZER, |
94 | SR_HWCAP_SAMPLERATE, | |
95 | SR_HWCAP_CAPTURE_RATIO, | |
96 | SR_HWCAP_PROBECONFIG, | |
28a35d8a | 97 | |
5a2326a7 | 98 | SR_HWCAP_LIMIT_MSEC, |
28a35d8a HE |
99 | 0, |
100 | }; | |
101 | ||
fefa1800 UH |
102 | /* Force the FPGA to reboot. */ |
103 | static uint8_t suicide[] = { | |
104 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
105 | }; | |
106 | ||
107 | /* Prepare to upload firmware (FPGA specific). */ | |
108 | static uint8_t init[] = { | |
109 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
110 | }; | |
111 | ||
112 | /* Initialize the logic analyzer mode. */ | |
113 | static uint8_t logic_mode_start[] = { | |
114 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
115 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
116 | }; | |
117 | ||
eec5275e | 118 | static const char *firmware_files[] = { |
a8116d76 HE |
119 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
120 | "asix-sigma-100.fw", /* 100 MHz */ | |
121 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 122 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 123 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
124 | }; |
125 | ||
3cd3a20b | 126 | static int hw_dev_acquisition_stop(int dev_index, void *cb_data); |
6aac7737 | 127 | |
ea9cfed7 | 128 | static int sigma_read(void *buf, size_t size, struct context *ctx) |
28a35d8a HE |
129 | { |
130 | int ret; | |
fefa1800 | 131 | |
ea9cfed7 | 132 | ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size); |
28a35d8a | 133 | if (ret < 0) { |
7b48d6e1 | 134 | sr_err("sigma: ftdi_read_data failed: %s", |
ea9cfed7 | 135 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
136 | } |
137 | ||
138 | return ret; | |
139 | } | |
140 | ||
ea9cfed7 | 141 | static int sigma_write(void *buf, size_t size, struct context *ctx) |
28a35d8a HE |
142 | { |
143 | int ret; | |
fefa1800 | 144 | |
ea9cfed7 | 145 | ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size); |
28a35d8a | 146 | if (ret < 0) { |
7b48d6e1 | 147 | sr_err("sigma: ftdi_write_data failed: %s", |
ea9cfed7 | 148 | ftdi_get_error_string(&ctx->ftdic)); |
fefa1800 | 149 | } else if ((size_t) ret != size) { |
7b48d6e1 | 150 | sr_err("sigma: ftdi_write_data did not complete write\n"); |
28a35d8a HE |
151 | } |
152 | ||
153 | return ret; | |
154 | } | |
155 | ||
99965709 | 156 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
ea9cfed7 | 157 | struct context *ctx) |
28a35d8a HE |
158 | { |
159 | size_t i; | |
160 | uint8_t buf[len + 2]; | |
161 | int idx = 0; | |
162 | ||
163 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
164 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
165 | ||
fefa1800 | 166 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
167 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
168 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
169 | } | |
170 | ||
ea9cfed7 | 171 | return sigma_write(buf, idx, ctx); |
28a35d8a HE |
172 | } |
173 | ||
ea9cfed7 | 174 | static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx) |
28a35d8a | 175 | { |
ea9cfed7 | 176 | return sigma_write_register(reg, &value, 1, ctx); |
28a35d8a HE |
177 | } |
178 | ||
99965709 | 179 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
ea9cfed7 | 180 | struct context *ctx) |
28a35d8a HE |
181 | { |
182 | uint8_t buf[3]; | |
fefa1800 | 183 | |
28a35d8a HE |
184 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
185 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
186 | buf[2] = REG_READ_ADDR; |
187 | ||
ea9cfed7 | 188 | sigma_write(buf, sizeof(buf), ctx); |
28a35d8a | 189 | |
ea9cfed7 | 190 | return sigma_read(data, len, ctx); |
28a35d8a HE |
191 | } |
192 | ||
ea9cfed7 | 193 | static uint8_t sigma_get_register(uint8_t reg, struct context *ctx) |
28a35d8a HE |
194 | { |
195 | uint8_t value; | |
fefa1800 | 196 | |
ea9cfed7 | 197 | if (1 != sigma_read_register(reg, &value, 1, ctx)) { |
7b48d6e1 | 198 | sr_err("sigma: sigma_get_register: 1 byte expected"); |
28a35d8a HE |
199 | return 0; |
200 | } | |
201 | ||
202 | return value; | |
203 | } | |
204 | ||
99965709 | 205 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
ea9cfed7 | 206 | struct context *ctx) |
28a35d8a HE |
207 | { |
208 | uint8_t buf[] = { | |
209 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
210 | ||
211 | REG_READ_ADDR | NEXT_REG, | |
212 | REG_READ_ADDR | NEXT_REG, | |
213 | REG_READ_ADDR | NEXT_REG, | |
214 | REG_READ_ADDR | NEXT_REG, | |
215 | REG_READ_ADDR | NEXT_REG, | |
216 | REG_READ_ADDR | NEXT_REG, | |
217 | }; | |
28a35d8a HE |
218 | uint8_t result[6]; |
219 | ||
ea9cfed7 | 220 | sigma_write(buf, sizeof(buf), ctx); |
28a35d8a | 221 | |
ea9cfed7 | 222 | sigma_read(result, sizeof(result), ctx); |
28a35d8a HE |
223 | |
224 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
225 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
226 | ||
57bbf56b HE |
227 | /* Not really sure why this must be done, but according to spec. */ |
228 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
229 | stoppos -= 64; | |
230 | ||
231 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
232 | triggerpos -= 64; | |
233 | ||
28a35d8a HE |
234 | return 1; |
235 | } | |
236 | ||
99965709 | 237 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
ea9cfed7 | 238 | uint8_t *data, struct context *ctx) |
28a35d8a HE |
239 | { |
240 | size_t i; | |
241 | uint8_t buf[4096]; | |
242 | int idx = 0; | |
243 | ||
fefa1800 | 244 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
245 | buf[0] = startchunk >> 8; |
246 | buf[1] = startchunk & 0xff; | |
ea9cfed7 | 247 | sigma_write_register(WRITE_MEMROW, buf, 2, ctx); |
28a35d8a | 248 | |
fefa1800 | 249 | /* Read the DRAM. */ |
28a35d8a HE |
250 | buf[idx++] = REG_DRAM_BLOCK; |
251 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
252 | ||
253 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
254 | /* Alternate bit to copy from DRAM to cache. */ |
255 | if (i != (numchunks - 1)) | |
256 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
257 | |
258 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
259 | ||
fefa1800 | 260 | if (i != (numchunks - 1)) |
28a35d8a HE |
261 | buf[idx++] = REG_DRAM_WAIT_ACK; |
262 | } | |
263 | ||
ea9cfed7 | 264 | sigma_write(buf, idx, ctx); |
28a35d8a | 265 | |
ea9cfed7 | 266 | return sigma_read(data, numchunks * CHUNK_SIZE, ctx); |
28a35d8a HE |
267 | } |
268 | ||
4ae1f451 | 269 | /* Upload trigger look-up tables to Sigma. */ |
ea9cfed7 | 270 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx) |
ee492173 HE |
271 | { |
272 | int i; | |
273 | uint8_t tmp[2]; | |
274 | uint16_t bit; | |
275 | ||
276 | /* Transpose the table and send to Sigma. */ | |
277 | for (i = 0; i < 16; ++i) { | |
278 | bit = 1 << i; | |
279 | ||
280 | tmp[0] = tmp[1] = 0; | |
281 | ||
282 | if (lut->m2d[0] & bit) | |
283 | tmp[0] |= 0x01; | |
284 | if (lut->m2d[1] & bit) | |
285 | tmp[0] |= 0x02; | |
286 | if (lut->m2d[2] & bit) | |
287 | tmp[0] |= 0x04; | |
288 | if (lut->m2d[3] & bit) | |
289 | tmp[0] |= 0x08; | |
290 | ||
291 | if (lut->m3 & bit) | |
292 | tmp[0] |= 0x10; | |
293 | if (lut->m3s & bit) | |
294 | tmp[0] |= 0x20; | |
295 | if (lut->m4 & bit) | |
296 | tmp[0] |= 0x40; | |
297 | ||
298 | if (lut->m0d[0] & bit) | |
299 | tmp[1] |= 0x01; | |
300 | if (lut->m0d[1] & bit) | |
301 | tmp[1] |= 0x02; | |
302 | if (lut->m0d[2] & bit) | |
303 | tmp[1] |= 0x04; | |
304 | if (lut->m0d[3] & bit) | |
305 | tmp[1] |= 0x08; | |
306 | ||
307 | if (lut->m1d[0] & bit) | |
308 | tmp[1] |= 0x10; | |
309 | if (lut->m1d[1] & bit) | |
310 | tmp[1] |= 0x20; | |
311 | if (lut->m1d[2] & bit) | |
312 | tmp[1] |= 0x40; | |
313 | if (lut->m1d[3] & bit) | |
314 | tmp[1] |= 0x80; | |
315 | ||
99965709 | 316 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
ea9cfed7 UH |
317 | ctx); |
318 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx); | |
ee492173 HE |
319 | } |
320 | ||
321 | /* Send the parameters */ | |
322 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
ea9cfed7 | 323 | sizeof(lut->params), ctx); |
ee492173 | 324 | |
e46b8fb1 | 325 | return SR_OK; |
ee492173 HE |
326 | } |
327 | ||
fefa1800 | 328 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 329 | static int bin2bitbang(const char *filename, |
fefa1800 | 330 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 331 | { |
fefa1800 | 332 | FILE *f; |
28a35d8a HE |
333 | long file_size; |
334 | unsigned long offset = 0; | |
335 | unsigned char *p; | |
336 | uint8_t *compressed_buf, *firmware; | |
337 | uLongf csize, fwsize; | |
338 | const int buffer_size = 65536; | |
339 | size_t i; | |
fefa1800 UH |
340 | int c, ret, bit, v; |
341 | uint32_t imm = 0x3f6df2ab; | |
28a35d8a | 342 | |
868d8cef | 343 | f = g_fopen(filename, "rb"); |
28a35d8a | 344 | if (!f) { |
7b48d6e1 | 345 | sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 346 | return SR_ERR; |
28a35d8a HE |
347 | } |
348 | ||
349 | if (-1 == fseek(f, 0, SEEK_END)) { | |
7b48d6e1 | 350 | sr_err("sigma: fseek on %s failed", filename); |
28a35d8a | 351 | fclose(f); |
b53738ba | 352 | return SR_ERR; |
28a35d8a HE |
353 | } |
354 | ||
355 | file_size = ftell(f); | |
356 | ||
357 | fseek(f, 0, SEEK_SET); | |
358 | ||
b53738ba | 359 | if (!(compressed_buf = g_try_malloc(file_size))) { |
340cfac0 | 360 | sr_err("sigma: %s: compressed_buf malloc failed", __func__); |
12ad53f5 | 361 | fclose(f); |
b53738ba UH |
362 | return SR_ERR_MALLOC; |
363 | } | |
28a35d8a | 364 | |
b53738ba | 365 | if (!(firmware = g_try_malloc(buffer_size))) { |
340cfac0 | 366 | sr_err("sigma: %s: firmware malloc failed", __func__); |
12ad53f5 UH |
367 | fclose(f); |
368 | g_free(compressed_buf); | |
b53738ba | 369 | return SR_ERR_MALLOC; |
28a35d8a HE |
370 | } |
371 | ||
28a35d8a HE |
372 | csize = 0; |
373 | while ((c = getc(f)) != EOF) { | |
374 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
375 | compressed_buf[csize++] = c ^ imm; | |
376 | } | |
377 | fclose(f); | |
378 | ||
379 | fwsize = buffer_size; | |
380 | ret = uncompress(firmware, &fwsize, compressed_buf, csize); | |
381 | if (ret < 0) { | |
382 | g_free(compressed_buf); | |
383 | g_free(firmware); | |
7b48d6e1 UH |
384 | sr_err("sigma: Could not unpack Sigma firmware. " |
385 | "(Error %d)\n", ret); | |
b53738ba | 386 | return SR_ERR; |
28a35d8a HE |
387 | } |
388 | ||
389 | g_free(compressed_buf); | |
390 | ||
391 | *buf_size = fwsize * 2 * 8; | |
392 | ||
b53738ba | 393 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 394 | if (!p) { |
340cfac0 | 395 | sr_err("sigma: %s: buf/p malloc failed", __func__); |
12ad53f5 UH |
396 | g_free(compressed_buf); |
397 | g_free(firmware); | |
b53738ba | 398 | return SR_ERR_MALLOC; |
28a35d8a HE |
399 | } |
400 | ||
401 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 402 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 403 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
404 | p[offset++] = v | 0x01; |
405 | p[offset++] = v; | |
406 | } | |
407 | } | |
408 | ||
409 | g_free(firmware); | |
410 | ||
411 | if (offset != *buf_size) { | |
412 | g_free(*buf); | |
7b48d6e1 | 413 | sr_err("sigma: Error reading firmware %s " |
133a37bf UH |
414 | "offset=%ld, file_size=%ld, buf_size=%zd\n", |
415 | filename, offset, file_size, *buf_size); | |
28a35d8a | 416 | |
b53738ba | 417 | return SR_ERR; |
28a35d8a HE |
418 | } |
419 | ||
b53738ba | 420 | return SR_OK; |
28a35d8a HE |
421 | } |
422 | ||
bb7ef793 | 423 | static int hw_init(const char *devinfo) |
28a35d8a | 424 | { |
d68e2d1a | 425 | struct sr_dev_inst *sdi; |
ea9cfed7 | 426 | struct context *ctx; |
28a35d8a | 427 | |
b53738ba | 428 | /* Avoid compiler warnings. */ |
bb7ef793 | 429 | (void)devinfo; |
28a35d8a | 430 | |
ea9cfed7 UH |
431 | if (!(ctx = g_try_malloc(sizeof(struct context)))) { |
432 | sr_err("sigma: %s: ctx malloc failed", __func__); | |
b53738ba UH |
433 | return 0; /* FIXME: Should be SR_ERR_MALLOC. */ |
434 | } | |
99965709 | 435 | |
ea9cfed7 | 436 | ftdi_init(&ctx->ftdic); |
28a35d8a | 437 | |
fefa1800 | 438 | /* Look for SIGMAs. */ |
ea9cfed7 | 439 | if (ftdi_usb_open_desc(&ctx->ftdic, USB_VENDOR, USB_PRODUCT, |
fefa1800 | 440 | USB_DESCRIPTION, NULL) < 0) |
99965709 HE |
441 | goto free; |
442 | ||
ea9cfed7 UH |
443 | ctx->cur_samplerate = 0; |
444 | ctx->period_ps = 0; | |
445 | ctx->limit_msec = 0; | |
446 | ctx->cur_firmware = -1; | |
447 | ctx->num_probes = 0; | |
448 | ctx->samples_per_event = 0; | |
449 | ctx->capture_ratio = 50; | |
450 | ctx->use_triggers = 0; | |
28a35d8a | 451 | |
fefa1800 | 452 | /* Register SIGMA device. */ |
d68e2d1a UH |
453 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
454 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
455 | sr_err("sigma: %s: sdi was NULL", __func__); | |
99965709 | 456 | goto free; |
d68e2d1a | 457 | } |
99965709 | 458 | |
ea9cfed7 | 459 | sdi->priv = ctx; |
28a35d8a | 460 | |
d68e2d1a | 461 | dev_insts = g_slist_append(dev_insts, sdi); |
28a35d8a | 462 | |
fefa1800 | 463 | /* We will open the device again when we need it. */ |
ea9cfed7 | 464 | ftdi_usb_close(&ctx->ftdic); |
28a35d8a HE |
465 | |
466 | return 1; | |
ea9cfed7 | 467 | |
99965709 | 468 | free: |
ea9cfed7 | 469 | g_free(ctx); |
99965709 | 470 | return 0; |
28a35d8a HE |
471 | } |
472 | ||
ea9cfed7 | 473 | static int upload_firmware(int firmware_idx, struct context *ctx) |
28a35d8a HE |
474 | { |
475 | int ret; | |
476 | unsigned char *buf; | |
477 | unsigned char pins; | |
478 | size_t buf_size; | |
28a35d8a | 479 | unsigned char result[32]; |
e8397563 | 480 | char firmware_path[128]; |
28a35d8a | 481 | |
fefa1800 | 482 | /* Make sure it's an ASIX SIGMA. */ |
ea9cfed7 | 483 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, |
28a35d8a | 484 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
7b48d6e1 | 485 | sr_err("sigma: ftdi_usb_open failed: %s", |
ea9cfed7 | 486 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
487 | return 0; |
488 | } | |
489 | ||
ea9cfed7 | 490 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
7b48d6e1 | 491 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
ea9cfed7 | 492 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
493 | return 0; |
494 | } | |
495 | ||
fefa1800 | 496 | /* Four times the speed of sigmalogan - Works well. */ |
ea9cfed7 | 497 | if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) { |
7b48d6e1 | 498 | sr_err("sigma: ftdi_set_baudrate failed: %s", |
ea9cfed7 | 499 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
500 | return 0; |
501 | } | |
502 | ||
fefa1800 | 503 | /* Force the FPGA to reboot. */ |
ea9cfed7 UH |
504 | sigma_write(suicide, sizeof(suicide), ctx); |
505 | sigma_write(suicide, sizeof(suicide), ctx); | |
506 | sigma_write(suicide, sizeof(suicide), ctx); | |
507 | sigma_write(suicide, sizeof(suicide), ctx); | |
28a35d8a | 508 | |
fefa1800 | 509 | /* Prepare to upload firmware (FPGA specific). */ |
ea9cfed7 | 510 | sigma_write(init, sizeof(init), ctx); |
28a35d8a | 511 | |
ea9cfed7 | 512 | ftdi_usb_purge_buffers(&ctx->ftdic); |
28a35d8a | 513 | |
fefa1800 | 514 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 515 | while (1) { |
ea9cfed7 | 516 | ret = sigma_read(result, 1, ctx); |
28a35d8a HE |
517 | if (result[0] & 0x20) |
518 | break; | |
519 | } | |
520 | ||
9ddb2a12 | 521 | /* Prepare firmware. */ |
e8397563 | 522 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
523 | firmware_files[firmware_idx]); |
524 | ||
b53738ba | 525 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { |
7b48d6e1 | 526 | sr_err("sigma: An error occured while reading the firmware: %s", |
133a37bf | 527 | firmware_path); |
b53738ba | 528 | return ret; |
28a35d8a HE |
529 | } |
530 | ||
fefa1800 | 531 | /* Upload firmare. */ |
ea9cfed7 | 532 | sigma_write(buf, buf_size, ctx); |
28a35d8a HE |
533 | |
534 | g_free(buf); | |
535 | ||
ea9cfed7 | 536 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) { |
7b48d6e1 | 537 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
ea9cfed7 | 538 | ftdi_get_error_string(&ctx->ftdic)); |
e46b8fb1 | 539 | return SR_ERR; |
28a35d8a HE |
540 | } |
541 | ||
ea9cfed7 | 542 | ftdi_usb_purge_buffers(&ctx->ftdic); |
28a35d8a | 543 | |
fefa1800 | 544 | /* Discard garbage. */ |
ea9cfed7 | 545 | while (1 == sigma_read(&pins, 1, ctx)) |
28a35d8a HE |
546 | ; |
547 | ||
fefa1800 | 548 | /* Initialize the logic analyzer mode. */ |
ea9cfed7 | 549 | sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx); |
28a35d8a | 550 | |
fefa1800 | 551 | /* Expect a 3 byte reply. */ |
ea9cfed7 | 552 | ret = sigma_read(result, 3, ctx); |
28a35d8a HE |
553 | if (ret != 3 || |
554 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
7b48d6e1 | 555 | sr_err("sigma: Configuration failed. Invalid reply received."); |
e46b8fb1 | 556 | return SR_ERR; |
28a35d8a HE |
557 | } |
558 | ||
ea9cfed7 | 559 | ctx->cur_firmware = firmware_idx; |
f6564c8d | 560 | |
e46b8fb1 | 561 | return SR_OK; |
f6564c8d HE |
562 | } |
563 | ||
e7eb703f | 564 | static int hw_dev_open(int dev_index) |
f6564c8d | 565 | { |
d68e2d1a | 566 | struct sr_dev_inst *sdi; |
ea9cfed7 | 567 | struct context *ctx; |
f6564c8d HE |
568 | int ret; |
569 | ||
bb7ef793 | 570 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 571 | return SR_ERR; |
99965709 | 572 | |
ea9cfed7 | 573 | ctx = sdi->priv; |
99965709 | 574 | |
9ddb2a12 | 575 | /* Make sure it's an ASIX SIGMA. */ |
ea9cfed7 | 576 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, |
f6564c8d HE |
577 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
578 | ||
7b48d6e1 | 579 | sr_err("sigma: ftdi_usb_open failed: %s", |
ea9cfed7 | 580 | ftdi_get_error_string(&ctx->ftdic)); |
f6564c8d HE |
581 | |
582 | return 0; | |
583 | } | |
28a35d8a | 584 | |
5a2326a7 | 585 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 586 | |
e46b8fb1 | 587 | return SR_OK; |
f6564c8d HE |
588 | } |
589 | ||
d68e2d1a | 590 | static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 591 | { |
e8397563 | 592 | int i, ret; |
ea9cfed7 | 593 | struct context *ctx = sdi->priv; |
f6564c8d HE |
594 | |
595 | for (i = 0; supported_samplerates[i]; i++) { | |
596 | if (supported_samplerates[i] == samplerate) | |
597 | break; | |
598 | } | |
599 | if (supported_samplerates[i] == 0) | |
e46b8fb1 | 600 | return SR_ERR_SAMPLERATE; |
f6564c8d | 601 | |
59df0c77 | 602 | if (samplerate <= SR_MHZ(50)) { |
ea9cfed7 UH |
603 | ret = upload_firmware(0, ctx); |
604 | ctx->num_probes = 16; | |
e8397563 | 605 | } |
59df0c77 | 606 | if (samplerate == SR_MHZ(100)) { |
ea9cfed7 UH |
607 | ret = upload_firmware(1, ctx); |
608 | ctx->num_probes = 8; | |
f78898e9 | 609 | } |
59df0c77 | 610 | else if (samplerate == SR_MHZ(200)) { |
ea9cfed7 UH |
611 | ret = upload_firmware(2, ctx); |
612 | ctx->num_probes = 4; | |
f78898e9 | 613 | } |
f6564c8d | 614 | |
ea9cfed7 UH |
615 | ctx->cur_samplerate = samplerate; |
616 | ctx->period_ps = 1000000000000 / samplerate; | |
617 | ctx->samples_per_event = 16 / ctx->num_probes; | |
618 | ctx->state.state = SIGMA_IDLE; | |
f6564c8d | 619 | |
7b48d6e1 | 620 | sr_info("sigma: Firmware uploaded"); |
28a35d8a | 621 | |
e8397563 | 622 | return ret; |
28a35d8a HE |
623 | } |
624 | ||
c53d793f HE |
625 | /* |
626 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
627 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
628 | * in addition to value/mask trigger for any number of probes. | |
629 | * | |
630 | * The Sigma supports complex triggers using boolean expressions, but this | |
631 | * has not been implemented yet. | |
632 | */ | |
d68e2d1a | 633 | static int configure_probes(struct sr_dev_inst *sdi, GSList *probes) |
57bbf56b | 634 | { |
ea9cfed7 | 635 | struct context *ctx = sdi->priv; |
1afe8989 | 636 | struct sr_probe *probe; |
57bbf56b HE |
637 | GSList *l; |
638 | int trigger_set = 0; | |
a42aec7f | 639 | int probebit; |
57bbf56b | 640 | |
ea9cfed7 | 641 | memset(&ctx->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 642 | |
57bbf56b | 643 | for (l = probes; l; l = l->next) { |
1afe8989 | 644 | probe = (struct sr_probe *)l->data; |
a42aec7f | 645 | probebit = 1 << (probe->index - 1); |
57bbf56b HE |
646 | |
647 | if (!probe->enabled || !probe->trigger) | |
648 | continue; | |
649 | ||
ea9cfed7 | 650 | if (ctx->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 651 | /* Fast trigger support. */ |
ee492173 | 652 | if (trigger_set) { |
7b48d6e1 | 653 | sr_err("sigma: ASIX SIGMA only supports a single " |
133a37bf | 654 | "pin trigger in 100 and 200MHz mode."); |
e46b8fb1 | 655 | return SR_ERR; |
ee492173 HE |
656 | } |
657 | if (probe->trigger[0] == 'f') | |
ea9cfed7 | 658 | ctx->trigger.fallingmask |= probebit; |
ee492173 | 659 | else if (probe->trigger[0] == 'r') |
ea9cfed7 | 660 | ctx->trigger.risingmask |= probebit; |
ee492173 | 661 | else { |
7b48d6e1 | 662 | sr_err("sigma: ASIX SIGMA only supports " |
133a37bf UH |
663 | "rising/falling trigger in 100 " |
664 | "and 200MHz mode."); | |
e46b8fb1 | 665 | return SR_ERR; |
ee492173 | 666 | } |
57bbf56b | 667 | |
c53d793f | 668 | ++trigger_set; |
ee492173 | 669 | } else { |
c53d793f HE |
670 | /* Simple trigger support (event). */ |
671 | if (probe->trigger[0] == '1') { | |
ea9cfed7 UH |
672 | ctx->trigger.simplevalue |= probebit; |
673 | ctx->trigger.simplemask |= probebit; | |
c53d793f HE |
674 | } |
675 | else if (probe->trigger[0] == '0') { | |
ea9cfed7 UH |
676 | ctx->trigger.simplevalue &= ~probebit; |
677 | ctx->trigger.simplemask |= probebit; | |
c53d793f HE |
678 | } |
679 | else if (probe->trigger[0] == 'f') { | |
ea9cfed7 | 680 | ctx->trigger.fallingmask |= probebit; |
c53d793f HE |
681 | ++trigger_set; |
682 | } | |
683 | else if (probe->trigger[0] == 'r') { | |
ea9cfed7 | 684 | ctx->trigger.risingmask |= probebit; |
c53d793f HE |
685 | ++trigger_set; |
686 | } | |
ee492173 | 687 | |
ea9cfed7 UH |
688 | /* |
689 | * Actually, Sigma supports 2 rising/falling triggers, | |
690 | * but they are ORed and the current trigger syntax | |
691 | * does not permit ORed triggers. | |
692 | */ | |
98b8cbc1 | 693 | if (trigger_set > 1) { |
7b48d6e1 UH |
694 | sr_err("sigma: ASIX SIGMA only supports 1 " |
695 | "rising/falling triggers."); | |
e46b8fb1 | 696 | return SR_ERR; |
ee492173 | 697 | } |
ee492173 | 698 | } |
5b5ea7c6 HE |
699 | |
700 | if (trigger_set) | |
ea9cfed7 | 701 | ctx->use_triggers = 1; |
57bbf56b HE |
702 | } |
703 | ||
e46b8fb1 | 704 | return SR_OK; |
57bbf56b HE |
705 | } |
706 | ||
e7eb703f | 707 | static int hw_dev_close(int dev_index) |
28a35d8a | 708 | { |
d68e2d1a | 709 | struct sr_dev_inst *sdi; |
ea9cfed7 | 710 | struct context *ctx; |
28a35d8a | 711 | |
bb7ef793 | 712 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
340cfac0 | 713 | sr_err("sigma: %s: sdi was NULL", __func__); |
0abee507 | 714 | return SR_ERR_BUG; |
697785d1 | 715 | } |
9be9893e | 716 | |
ea9cfed7 | 717 | if (!(ctx = sdi->priv)) { |
340cfac0 | 718 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
0abee507 | 719 | return SR_ERR_BUG; |
9be9893e | 720 | } |
697785d1 UH |
721 | |
722 | /* TODO */ | |
723 | if (sdi->status == SR_ST_ACTIVE) | |
ea9cfed7 | 724 | ftdi_usb_close(&ctx->ftdic); |
697785d1 UH |
725 | |
726 | sdi->status = SR_ST_INACTIVE; | |
727 | ||
728 | return SR_OK; | |
28a35d8a HE |
729 | } |
730 | ||
57ab7d9f | 731 | static int hw_cleanup(void) |
28a35d8a | 732 | { |
99965709 | 733 | GSList *l; |
d68e2d1a | 734 | struct sr_dev_inst *sdi; |
57ab7d9f | 735 | int ret = SR_OK; |
99965709 HE |
736 | |
737 | /* Properly close all devices. */ | |
d68e2d1a | 738 | for (l = dev_insts; l; l = l->next) { |
57ab7d9f UH |
739 | if (!(sdi = l->data)) { |
740 | /* Log error, but continue cleaning up the rest. */ | |
7b48d6e1 | 741 | sr_err("sigma: %s: sdi was NULL, continuing", __func__); |
57ab7d9f UH |
742 | ret = SR_ERR_BUG; |
743 | continue; | |
744 | } | |
d3683c42 | 745 | sr_dev_inst_free(sdi); |
99965709 | 746 | } |
d68e2d1a UH |
747 | g_slist_free(dev_insts); |
748 | dev_insts = NULL; | |
57ab7d9f UH |
749 | |
750 | return ret; | |
28a35d8a HE |
751 | } |
752 | ||
5097b0d0 | 753 | static void *hw_dev_info_get(int dev_index, int dev_info_id) |
28a35d8a | 754 | { |
d68e2d1a | 755 | struct sr_dev_inst *sdi; |
ea9cfed7 | 756 | struct context *ctx; |
28a35d8a HE |
757 | void *info = NULL; |
758 | ||
bb7ef793 | 759 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
7b48d6e1 | 760 | sr_err("sigma: %s: sdi was NULL", __func__); |
28a35d8a HE |
761 | return NULL; |
762 | } | |
763 | ||
ea9cfed7 | 764 | ctx = sdi->priv; |
99965709 | 765 | |
bb7ef793 | 766 | switch (dev_info_id) { |
1d9a8a5f | 767 | case SR_DI_INST: |
28a35d8a HE |
768 | info = sdi; |
769 | break; | |
5a2326a7 | 770 | case SR_DI_NUM_PROBES: |
464d12c7 KS |
771 | info = GINT_TO_POINTER(NUM_PROBES); |
772 | break; | |
773 | case SR_DI_PROBE_NAMES: | |
774 | info = probe_names; | |
28a35d8a | 775 | break; |
5a2326a7 | 776 | case SR_DI_SAMPLERATES: |
28a35d8a HE |
777 | info = &samplerates; |
778 | break; | |
5a2326a7 | 779 | case SR_DI_TRIGGER_TYPES: |
57bbf56b | 780 | info = (char *)TRIGGER_TYPES; |
28a35d8a | 781 | break; |
5a2326a7 | 782 | case SR_DI_CUR_SAMPLERATE: |
ea9cfed7 | 783 | info = &ctx->cur_samplerate; |
28a35d8a HE |
784 | break; |
785 | } | |
786 | ||
787 | return info; | |
788 | } | |
789 | ||
e7eb703f | 790 | static int hw_dev_status_get(int dev_index) |
28a35d8a | 791 | { |
d68e2d1a | 792 | struct sr_dev_inst *sdi; |
28a35d8a | 793 | |
bb7ef793 | 794 | sdi = sr_dev_inst_get(dev_insts, dev_index); |
28a35d8a HE |
795 | if (sdi) |
796 | return sdi->status; | |
797 | else | |
5a2326a7 | 798 | return SR_ST_NOT_FOUND; |
28a35d8a HE |
799 | } |
800 | ||
ffedd0bf | 801 | static int *hw_hwcap_get_all(void) |
28a35d8a | 802 | { |
ffedd0bf | 803 | return hwcaps; |
28a35d8a HE |
804 | } |
805 | ||
a9a245b4 | 806 | static int hw_dev_config_set(int dev_index, int hwcap, void *value) |
28a35d8a | 807 | { |
d68e2d1a | 808 | struct sr_dev_inst *sdi; |
ea9cfed7 | 809 | struct context *ctx; |
28a35d8a | 810 | int ret; |
f6564c8d | 811 | |
bb7ef793 | 812 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 813 | return SR_ERR; |
28a35d8a | 814 | |
ea9cfed7 | 815 | ctx = sdi->priv; |
99965709 | 816 | |
ffedd0bf | 817 | if (hwcap == SR_HWCAP_SAMPLERATE) { |
ea9cfed7 | 818 | ret = set_samplerate(sdi, *(uint64_t *)value); |
ffedd0bf | 819 | } else if (hwcap == SR_HWCAP_PROBECONFIG) { |
99965709 | 820 | ret = configure_probes(sdi, value); |
ffedd0bf | 821 | } else if (hwcap == SR_HWCAP_LIMIT_MSEC) { |
ea9cfed7 UH |
822 | ctx->limit_msec = *(uint64_t *)value; |
823 | if (ctx->limit_msec > 0) | |
e46b8fb1 | 824 | ret = SR_OK; |
94ba4bd6 | 825 | else |
e46b8fb1 | 826 | ret = SR_ERR; |
ffedd0bf | 827 | } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) { |
ea9cfed7 UH |
828 | ctx->capture_ratio = *(uint64_t *)value; |
829 | if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100) | |
e46b8fb1 | 830 | ret = SR_ERR; |
94ba4bd6 | 831 | else |
e46b8fb1 | 832 | ret = SR_OK; |
28a35d8a | 833 | } else { |
e46b8fb1 | 834 | ret = SR_ERR; |
28a35d8a HE |
835 | } |
836 | ||
837 | return ret; | |
838 | } | |
839 | ||
36b1c8e6 HE |
840 | /* Software trigger to determine exact trigger position. */ |
841 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
842 | struct sigma_trigger *t) | |
843 | { | |
844 | int i; | |
845 | ||
846 | for (i = 0; i < 8; ++i) { | |
847 | if (i > 0) | |
848 | last_sample = samples[i-1]; | |
849 | ||
850 | /* Simple triggers. */ | |
851 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
852 | continue; | |
853 | ||
854 | /* Rising edge. */ | |
855 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
856 | t->risingmask) != t->risingmask) | |
857 | continue; | |
858 | ||
859 | /* Falling edge. */ | |
bdfc7a89 HE |
860 | if ((last_sample & t->fallingmask) != t->fallingmask || |
861 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
862 | continue; |
863 | ||
864 | break; | |
865 | } | |
866 | ||
867 | /* If we did not match, return original trigger pos. */ | |
868 | return i & 0x7; | |
869 | } | |
870 | ||
28a35d8a | 871 | /* |
fefa1800 UH |
872 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
873 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
874 | * |
875 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
876 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
877 | * For 50 MHz and below, events contain one sample for each channel, | |
878 | * spread 20 ns apart. | |
28a35d8a HE |
879 | */ |
880 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 881 | uint16_t *lastsample, int triggerpos, |
3cd3a20b | 882 | uint16_t limit_chunk, void *cb_data) |
28a35d8a | 883 | { |
3cd3a20b | 884 | struct sr_dev_inst *sdi = cb_data; |
ea9cfed7 | 885 | struct context *ctx = sdi->priv; |
fefa1800 | 886 | uint16_t tsdiff, ts; |
ea9cfed7 | 887 | uint16_t samples[65536 * ctx->samples_per_event]; |
b9c735a2 | 888 | struct sr_datafeed_packet packet; |
9c939c51 | 889 | struct sr_datafeed_logic logic; |
f78898e9 | 890 | int i, j, k, l, numpad, tosend; |
fefa1800 | 891 | size_t n = 0, sent = 0; |
ea9cfed7 | 892 | int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event; |
fefa1800 | 893 | uint16_t *event; |
f78898e9 | 894 | uint16_t cur_sample; |
57bbf56b | 895 | int triggerts = -1; |
ee492173 | 896 | |
4ae1f451 | 897 | /* Check if trigger is in this chunk. */ |
ee492173 | 898 | if (triggerpos != -1) { |
ea9cfed7 | 899 | if (ctx->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 900 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
901 | |
902 | if (triggerpos < 0) | |
903 | triggerpos = 0; | |
57bbf56b | 904 | |
ee492173 HE |
905 | /* Find in which cluster the trigger occured. */ |
906 | triggerts = triggerpos / 7; | |
907 | } | |
28a35d8a | 908 | |
eec5275e | 909 | /* For each ts. */ |
28a35d8a | 910 | for (i = 0; i < 64; ++i) { |
fefa1800 | 911 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
912 | tsdiff = ts - *lastts; |
913 | *lastts = ts; | |
914 | ||
88c51afe HE |
915 | /* Decode partial chunk. */ |
916 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 917 | return SR_OK; |
88c51afe | 918 | |
fefa1800 | 919 | /* Pad last sample up to current point. */ |
ea9cfed7 | 920 | numpad = tsdiff * ctx->samples_per_event - clustersize; |
28a35d8a | 921 | if (numpad > 0) { |
f78898e9 HE |
922 | for (j = 0; j < numpad; ++j) |
923 | samples[j] = *lastsample; | |
924 | ||
925 | n = numpad; | |
28a35d8a HE |
926 | } |
927 | ||
57bbf56b HE |
928 | /* Send samples between previous and this timestamp to sigrok. */ |
929 | sent = 0; | |
930 | while (sent < n) { | |
931 | tosend = MIN(2048, n - sent); | |
932 | ||
5a2326a7 | 933 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
934 | packet.payload = &logic; |
935 | logic.length = tosend * sizeof(uint16_t); | |
936 | logic.unitsize = 2; | |
937 | logic.data = samples + sent; | |
3cd3a20b | 938 | sr_session_send(ctx->session_dev_id, &packet); |
28a35d8a | 939 | |
57bbf56b HE |
940 | sent += tosend; |
941 | } | |
942 | n = 0; | |
943 | ||
944 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
945 | cur_sample = 0; |
946 | ||
947 | /* For each event in cluster. */ | |
28a35d8a | 948 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
949 | |
950 | /* For each sample in event. */ | |
ea9cfed7 | 951 | for (k = 0; k < ctx->samples_per_event; ++k) { |
f78898e9 HE |
952 | cur_sample = 0; |
953 | ||
954 | /* For each probe. */ | |
ea9cfed7 | 955 | for (l = 0; l < ctx->num_probes; ++l) |
edca2c5c | 956 | cur_sample |= (!!(event[j] & (1 << (l * |
ea9cfed7 | 957 | ctx->samples_per_event + k)))) << l; |
f78898e9 HE |
958 | |
959 | samples[n++] = cur_sample; | |
28a35d8a HE |
960 | } |
961 | } | |
962 | ||
eec5275e | 963 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 964 | sent = 0; |
57bbf56b HE |
965 | if (i == triggerts) { |
966 | /* | |
36b1c8e6 HE |
967 | * Trigger is not always accurate to sample because of |
968 | * pipeline delay. However, it always triggers before | |
969 | * the actual event. We therefore look at the next | |
970 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 971 | */ |
bdfc7a89 | 972 | tosend = get_trigger_offset(samples, *lastsample, |
ea9cfed7 | 973 | &ctx->trigger); |
57bbf56b HE |
974 | |
975 | if (tosend > 0) { | |
5a2326a7 | 976 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
977 | packet.payload = &logic; |
978 | logic.length = tosend * sizeof(uint16_t); | |
979 | logic.unitsize = 2; | |
980 | logic.data = samples; | |
3cd3a20b | 981 | sr_session_send(ctx->session_dev_id, &packet); |
57bbf56b HE |
982 | |
983 | sent += tosend; | |
984 | } | |
28a35d8a | 985 | |
5b5ea7c6 | 986 | /* Only send trigger if explicitly enabled. */ |
ea9cfed7 | 987 | if (ctx->use_triggers) { |
5a2326a7 | 988 | packet.type = SR_DF_TRIGGER; |
3cd3a20b | 989 | sr_session_send(ctx->session_dev_id, &packet); |
5b5ea7c6 | 990 | } |
28a35d8a | 991 | } |
57bbf56b | 992 | |
eec5275e | 993 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
994 | tosend = n - sent; |
995 | ||
abda62ce | 996 | if (tosend > 0) { |
5a2326a7 | 997 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
998 | packet.payload = &logic; |
999 | logic.length = tosend * sizeof(uint16_t); | |
1000 | logic.unitsize = 2; | |
1001 | logic.data = samples + sent; | |
3cd3a20b | 1002 | sr_session_send(ctx->session_dev_id, &packet); |
abda62ce | 1003 | } |
ee492173 HE |
1004 | |
1005 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1006 | } |
1007 | ||
e46b8fb1 | 1008 | return SR_OK; |
28a35d8a HE |
1009 | } |
1010 | ||
1f9813eb | 1011 | static int receive_data(int fd, int revents, void *cb_data) |
28a35d8a | 1012 | { |
1f9813eb | 1013 | struct sr_dev_inst *sdi = cb_data; |
ea9cfed7 | 1014 | struct context *ctx = sdi->priv; |
b9c735a2 | 1015 | struct sr_datafeed_packet packet; |
28a35d8a HE |
1016 | const int chunks_per_read = 32; |
1017 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6aac7737 | 1018 | int bufsz, numchunks, i, newchunks; |
94ba4bd6 | 1019 | uint64_t running_msec; |
28a35d8a | 1020 | struct timeval tv; |
28a35d8a | 1021 | |
cb93f8a9 UH |
1022 | /* Avoid compiler warnings. */ |
1023 | (void)fd; | |
1024 | (void)revents; | |
28a35d8a | 1025 | |
ea9cfed7 | 1026 | numchunks = (ctx->state.stoppos + 511) / 512; |
28a35d8a | 1027 | |
ea9cfed7 | 1028 | if (ctx->state.state == SIGMA_IDLE) |
28a35d8a HE |
1029 | return FALSE; |
1030 | ||
ea9cfed7 | 1031 | if (ctx->state.state == SIGMA_CAPTURE) { |
6aac7737 HE |
1032 | /* Check if the timer has expired, or memory is full. */ |
1033 | gettimeofday(&tv, 0); | |
ea9cfed7 UH |
1034 | running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 + |
1035 | (tv.tv_usec - ctx->start_tv.tv_usec) / 1000; | |
28a35d8a | 1036 | |
ea9cfed7 | 1037 | if (running_msec < ctx->limit_msec && numchunks < 32767) |
6aac7737 | 1038 | return FALSE; |
28a35d8a | 1039 | |
1f9813eb | 1040 | hw_dev_acquisition_stop(sdi->index, sdi); |
6aac7737 HE |
1041 | |
1042 | return FALSE; | |
ea9cfed7 UH |
1043 | } else if (ctx->state.state == SIGMA_DOWNLOAD) { |
1044 | if (ctx->state.chunks_downloaded >= numchunks) { | |
6aac7737 | 1045 | /* End of samples. */ |
5a2326a7 | 1046 | packet.type = SR_DF_END; |
3cd3a20b | 1047 | sr_session_send(ctx->session_dev_id, &packet); |
6aac7737 | 1048 | |
ea9cfed7 | 1049 | ctx->state.state = SIGMA_IDLE; |
f78898e9 | 1050 | |
6aac7737 HE |
1051 | return TRUE; |
1052 | } | |
1053 | ||
1054 | newchunks = MIN(chunks_per_read, | |
ea9cfed7 | 1055 | numchunks - ctx->state.chunks_downloaded); |
28a35d8a | 1056 | |
7b48d6e1 | 1057 | sr_info("sigma: Downloading sample data: %.0f %%", |
ea9cfed7 | 1058 | 100.0 * ctx->state.chunks_downloaded / numchunks); |
28a35d8a | 1059 | |
ea9cfed7 UH |
1060 | bufsz = sigma_read_dram(ctx->state.chunks_downloaded, |
1061 | newchunks, buf, ctx); | |
719c5a93 UH |
1062 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1063 | (void)bufsz; | |
28a35d8a | 1064 | |
fefa1800 | 1065 | /* Find first ts. */ |
ea9cfed7 UH |
1066 | if (ctx->state.chunks_downloaded == 0) { |
1067 | ctx->state.lastts = *(uint16_t *) buf - 1; | |
1068 | ctx->state.lastsample = 0; | |
6aac7737 | 1069 | } |
28a35d8a | 1070 | |
fefa1800 | 1071 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 1072 | for (i = 0; i < newchunks; ++i) { |
88c51afe HE |
1073 | int limit_chunk = 0; |
1074 | ||
1075 | /* The last chunk may potentially be only in part. */ | |
ea9cfed7 | 1076 | if (ctx->state.chunks_downloaded == numchunks - 1) { |
88c51afe | 1077 | /* Find the last valid timestamp */ |
ea9cfed7 | 1078 | limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts; |
88c51afe HE |
1079 | } |
1080 | ||
ea9cfed7 | 1081 | if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk) |
57bbf56b | 1082 | decode_chunk_ts(buf + (i * CHUNK_SIZE), |
ea9cfed7 UH |
1083 | &ctx->state.lastts, |
1084 | &ctx->state.lastsample, | |
1085 | ctx->state.triggerpos & 0x1ff, | |
1f9813eb | 1086 | limit_chunk, sdi); |
57bbf56b HE |
1087 | else |
1088 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
ea9cfed7 UH |
1089 | &ctx->state.lastts, |
1090 | &ctx->state.lastsample, | |
1f9813eb | 1091 | -1, limit_chunk, sdi); |
28a35d8a | 1092 | |
ea9cfed7 | 1093 | ++ctx->state.chunks_downloaded; |
88c51afe | 1094 | } |
28a35d8a HE |
1095 | } |
1096 | ||
28a35d8a HE |
1097 | return TRUE; |
1098 | } | |
1099 | ||
c53d793f HE |
1100 | /* Build a LUT entry used by the trigger functions. */ |
1101 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1102 | { |
1103 | int i, j, k, bit; | |
1104 | ||
f758d074 | 1105 | /* For each quad probe. */ |
ee492173 | 1106 | for (i = 0; i < 4; ++i) { |
c53d793f | 1107 | entry[i] = 0xffff; |
ee492173 | 1108 | |
f758d074 | 1109 | /* For each bit in LUT. */ |
ee492173 HE |
1110 | for (j = 0; j < 16; ++j) |
1111 | ||
f758d074 | 1112 | /* For each probe in quad. */ |
ee492173 HE |
1113 | for (k = 0; k < 4; ++k) { |
1114 | bit = 1 << (i * 4 + k); | |
1115 | ||
c53d793f HE |
1116 | /* Set bit in entry */ |
1117 | if ((mask & bit) && | |
1118 | ((!(value & bit)) != | |
4ae1f451 | 1119 | (!(j & (1 << k))))) |
c53d793f | 1120 | entry[i] &= ~(1 << j); |
ee492173 HE |
1121 | } |
1122 | } | |
c53d793f | 1123 | } |
ee492173 | 1124 | |
c53d793f HE |
1125 | /* Add a logical function to LUT mask. */ |
1126 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1127 | int index, int neg, uint16_t *mask) | |
1128 | { | |
1129 | int i, j; | |
1130 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1131 | ||
1132 | memset(x, 0, 4 * sizeof(int)); | |
1133 | ||
1134 | /* Trigger detect condition. */ | |
1135 | switch (oper) { | |
1136 | case OP_LEVEL: | |
1137 | x[0][1] = 1; | |
1138 | x[1][1] = 1; | |
1139 | break; | |
1140 | case OP_NOT: | |
1141 | x[0][0] = 1; | |
1142 | x[1][0] = 1; | |
1143 | break; | |
1144 | case OP_RISE: | |
1145 | x[0][1] = 1; | |
1146 | break; | |
1147 | case OP_FALL: | |
1148 | x[1][0] = 1; | |
1149 | break; | |
1150 | case OP_RISEFALL: | |
1151 | x[0][1] = 1; | |
1152 | x[1][0] = 1; | |
1153 | break; | |
1154 | case OP_NOTRISE: | |
1155 | x[1][1] = 1; | |
1156 | x[0][0] = 1; | |
1157 | x[1][0] = 1; | |
1158 | break; | |
1159 | case OP_NOTFALL: | |
1160 | x[1][1] = 1; | |
1161 | x[0][0] = 1; | |
1162 | x[0][1] = 1; | |
1163 | break; | |
1164 | case OP_NOTRISEFALL: | |
1165 | x[1][1] = 1; | |
1166 | x[0][0] = 1; | |
1167 | break; | |
1168 | } | |
1169 | ||
1170 | /* Transpose if neg is set. */ | |
1171 | if (neg) { | |
ea9cfed7 | 1172 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1173 | for (j = 0; j < 2; ++j) { |
1174 | tmp = x[i][j]; | |
1175 | x[i][j] = x[1-i][1-j]; | |
1176 | x[1-i][1-j] = tmp; | |
1177 | } | |
ea9cfed7 | 1178 | } |
c53d793f HE |
1179 | } |
1180 | ||
1181 | /* Update mask with function. */ | |
1182 | for (i = 0; i < 16; ++i) { | |
1183 | a = (i >> (2 * index + 0)) & 1; | |
1184 | b = (i >> (2 * index + 1)) & 1; | |
1185 | ||
1186 | aset = (*mask >> i) & 1; | |
1187 | bset = x[b][a]; | |
1188 | ||
1189 | if (func == FUNC_AND || func == FUNC_NAND) | |
1190 | rset = aset & bset; | |
1191 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1192 | rset = aset | bset; | |
1193 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1194 | rset = aset ^ bset; | |
1195 | ||
1196 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1197 | rset = !rset; | |
1198 | ||
1199 | *mask &= ~(1 << i); | |
1200 | ||
1201 | if (rset) | |
1202 | *mask |= 1 << i; | |
1203 | } | |
1204 | } | |
1205 | ||
1206 | /* | |
1207 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1208 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1209 | * set at any time, but a full mask and value can be set (0/1). | |
1210 | */ | |
ea9cfed7 | 1211 | static int build_basic_trigger(struct triggerlut *lut, struct context *ctx) |
c53d793f HE |
1212 | { |
1213 | int i,j; | |
4ae1f451 | 1214 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1215 | |
1216 | memset(lut, 0, sizeof(struct triggerlut)); | |
1217 | ||
1218 | /* Contant for simple triggers. */ | |
1219 | lut->m4 = 0xa000; | |
1220 | ||
1221 | /* Value/mask trigger support. */ | |
ea9cfed7 | 1222 | build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask, |
99965709 | 1223 | lut->m2d); |
c53d793f HE |
1224 | |
1225 | /* Rise/fall trigger support. */ | |
1226 | for (i = 0, j = 0; i < 16; ++i) { | |
ea9cfed7 UH |
1227 | if (ctx->trigger.risingmask & (1 << i) || |
1228 | ctx->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1229 | masks[j++] = 1 << i; |
1230 | } | |
1231 | ||
1232 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1233 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1234 | ||
1235 | /* Add glue logic */ | |
1236 | if (masks[0] || masks[1]) { | |
1237 | /* Transition trigger. */ | |
ea9cfed7 | 1238 | if (masks[0] & ctx->trigger.risingmask) |
c53d793f | 1239 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
ea9cfed7 | 1240 | if (masks[0] & ctx->trigger.fallingmask) |
c53d793f | 1241 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
ea9cfed7 | 1242 | if (masks[1] & ctx->trigger.risingmask) |
c53d793f | 1243 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
ea9cfed7 | 1244 | if (masks[1] & ctx->trigger.fallingmask) |
c53d793f HE |
1245 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1246 | } else { | |
1247 | /* Only value/mask trigger. */ | |
1248 | lut->m3 = 0xffff; | |
1249 | } | |
ee492173 | 1250 | |
c53d793f | 1251 | /* Triggertype: event. */ |
ee492173 HE |
1252 | lut->params.selres = 3; |
1253 | ||
e46b8fb1 | 1254 | return SR_OK; |
ee492173 HE |
1255 | } |
1256 | ||
3cd3a20b | 1257 | static int hw_dev_acquisition_start(int dev_index, void *cb_data) |
28a35d8a | 1258 | { |
d68e2d1a | 1259 | struct sr_dev_inst *sdi; |
ea9cfed7 | 1260 | struct context *ctx; |
b9c735a2 UH |
1261 | struct sr_datafeed_packet packet; |
1262 | struct sr_datafeed_header header; | |
9ddb2a12 | 1263 | struct clockselect_50 clockselect; |
82957b65 | 1264 | int frac, triggerpin, ret; |
57bbf56b HE |
1265 | uint8_t triggerselect; |
1266 | struct triggerinout triggerinout_conf; | |
ee492173 | 1267 | struct triggerlut lut; |
28a35d8a | 1268 | |
bb7ef793 | 1269 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 1270 | return SR_ERR; |
28a35d8a | 1271 | |
ea9cfed7 | 1272 | ctx = sdi->priv; |
28a35d8a | 1273 | |
ea9cfed7 UH |
1274 | /* If the samplerate has not been set, default to 200 kHz. */ |
1275 | if (ctx->cur_firmware == -1) { | |
82957b65 UH |
1276 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1277 | return ret; | |
1278 | } | |
e8397563 | 1279 | |
eec5275e | 1280 | /* Enter trigger programming mode. */ |
ea9cfed7 | 1281 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx); |
28a35d8a | 1282 | |
eec5275e | 1283 | /* 100 and 200 MHz mode. */ |
ea9cfed7 UH |
1284 | if (ctx->cur_samplerate >= SR_MHZ(100)) { |
1285 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx); | |
57bbf56b | 1286 | |
a42aec7f HE |
1287 | /* Find which pin to trigger on from mask. */ |
1288 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
ea9cfed7 | 1289 | if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) & |
a42aec7f HE |
1290 | (1 << triggerpin)) |
1291 | break; | |
1292 | ||
1293 | /* Set trigger pin and light LED on trigger. */ | |
1294 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1295 | ||
1296 | /* Default rising edge. */ | |
ea9cfed7 | 1297 | if (ctx->trigger.fallingmask) |
a42aec7f | 1298 | triggerselect |= 1 << 3; |
57bbf56b | 1299 | |
eec5275e | 1300 | /* All other modes. */ |
ea9cfed7 UH |
1301 | } else if (ctx->cur_samplerate <= SR_MHZ(50)) { |
1302 | build_basic_trigger(&lut, ctx); | |
ee492173 | 1303 | |
ea9cfed7 | 1304 | sigma_write_trigger_lut(&lut, ctx); |
57bbf56b HE |
1305 | |
1306 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1307 | } | |
1308 | ||
eec5275e | 1309 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1310 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1311 | triggerinout_conf.trgout_bytrigger = 1; | |
1312 | triggerinout_conf.trgout_enable = 1; | |
1313 | ||
28a35d8a | 1314 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1315 | (uint8_t *) &triggerinout_conf, |
ea9cfed7 | 1316 | sizeof(struct triggerinout), ctx); |
28a35d8a | 1317 | |
eec5275e | 1318 | /* Go back to normal mode. */ |
ea9cfed7 | 1319 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx); |
28a35d8a | 1320 | |
edca2c5c | 1321 | /* Set clock select register. */ |
ea9cfed7 | 1322 | if (ctx->cur_samplerate == SR_MHZ(200)) |
edca2c5c | 1323 | /* Enable 4 probes. */ |
ea9cfed7 UH |
1324 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx); |
1325 | else if (ctx->cur_samplerate == SR_MHZ(100)) | |
edca2c5c | 1326 | /* Enable 8 probes. */ |
ea9cfed7 | 1327 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx); |
edca2c5c HE |
1328 | else { |
1329 | /* | |
9ddb2a12 | 1330 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1331 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1332 | */ |
ea9cfed7 | 1333 | frac = SR_MHZ(50) / ctx->cur_samplerate - 1; |
edca2c5c | 1334 | |
9ddb2a12 UH |
1335 | clockselect.async = 0; |
1336 | clockselect.fraction = frac; | |
1337 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
1338 | |
1339 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1340 | (uint8_t *) &clockselect, |
ea9cfed7 | 1341 | sizeof(clockselect), ctx); |
edca2c5c HE |
1342 | } |
1343 | ||
fefa1800 | 1344 | /* Setup maximum post trigger time. */ |
99965709 | 1345 | sigma_set_register(WRITE_POST_TRIGGER, |
ea9cfed7 | 1346 | (ctx->capture_ratio * 255) / 100, ctx); |
28a35d8a | 1347 | |
eec5275e | 1348 | /* Start acqusition. */ |
ea9cfed7 UH |
1349 | gettimeofday(&ctx->start_tv, 0); |
1350 | sigma_set_register(WRITE_MODE, 0x0d, ctx); | |
99965709 | 1351 | |
3cd3a20b | 1352 | ctx->session_dev_id = cb_data; |
28a35d8a | 1353 | |
28a35d8a | 1354 | /* Send header packet to the session bus. */ |
5a2326a7 | 1355 | packet.type = SR_DF_HEADER; |
28a35d8a HE |
1356 | packet.payload = &header; |
1357 | header.feed_version = 1; | |
1358 | gettimeofday(&header.starttime, NULL); | |
ea9cfed7 UH |
1359 | header.samplerate = ctx->cur_samplerate; |
1360 | header.num_logic_probes = ctx->num_probes; | |
3cd3a20b | 1361 | sr_session_send(ctx->session_dev_id, &packet); |
28a35d8a | 1362 | |
57bbf56b | 1363 | /* Add capture source. */ |
6f1be0a2 | 1364 | sr_source_add(0, G_IO_IN, 10, receive_data, sdi); |
57bbf56b | 1365 | |
ea9cfed7 | 1366 | ctx->state.state = SIGMA_CAPTURE; |
6aac7737 | 1367 | |
e46b8fb1 | 1368 | return SR_OK; |
28a35d8a HE |
1369 | } |
1370 | ||
3cd3a20b | 1371 | static int hw_dev_acquisition_stop(int dev_index, void *cb_data) |
28a35d8a | 1372 | { |
d68e2d1a | 1373 | struct sr_dev_inst *sdi; |
ea9cfed7 | 1374 | struct context *ctx; |
6aac7737 HE |
1375 | uint8_t modestatus; |
1376 | ||
cb93f8a9 | 1377 | /* Avoid compiler warnings. */ |
3cd3a20b | 1378 | (void)cb_data; |
28a35d8a | 1379 | |
bb7ef793 | 1380 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
7b48d6e1 | 1381 | sr_err("sigma: %s: sdi was NULL", __func__); |
3010f21c UH |
1382 | return SR_ERR_BUG; |
1383 | } | |
1384 | ||
ea9cfed7 | 1385 | if (!(ctx = sdi->priv)) { |
7b48d6e1 | 1386 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
3010f21c UH |
1387 | return SR_ERR_BUG; |
1388 | } | |
1389 | ||
fefa1800 | 1390 | /* Stop acquisition. */ |
ea9cfed7 | 1391 | sigma_set_register(WRITE_MODE, 0x11, ctx); |
28a35d8a | 1392 | |
6aac7737 | 1393 | /* Set SDRAM Read Enable. */ |
ea9cfed7 | 1394 | sigma_set_register(WRITE_MODE, 0x02, ctx); |
6aac7737 HE |
1395 | |
1396 | /* Get the current position. */ | |
ea9cfed7 | 1397 | sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx); |
6aac7737 HE |
1398 | |
1399 | /* Check if trigger has fired. */ | |
ea9cfed7 | 1400 | modestatus = sigma_get_register(READ_MODE, ctx); |
3010f21c | 1401 | if (modestatus & 0x20) |
ea9cfed7 | 1402 | ctx->state.triggerchunk = ctx->state.triggerpos / 512; |
3010f21c | 1403 | else |
ea9cfed7 | 1404 | ctx->state.triggerchunk = -1; |
6aac7737 | 1405 | |
ea9cfed7 | 1406 | ctx->state.chunks_downloaded = 0; |
6aac7737 | 1407 | |
ea9cfed7 | 1408 | ctx->state.state = SIGMA_DOWNLOAD; |
3010f21c UH |
1409 | |
1410 | return SR_OK; | |
28a35d8a HE |
1411 | } |
1412 | ||
c09f0b57 | 1413 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 UH |
1414 | .name = "asix-sigma", |
1415 | .longname = "ASIX SIGMA", | |
1416 | .api_version = 1, | |
1417 | .init = hw_init, | |
1418 | .cleanup = hw_cleanup, | |
e7eb703f UH |
1419 | .dev_open = hw_dev_open, |
1420 | .dev_close = hw_dev_close, | |
5097b0d0 | 1421 | .dev_info_get = hw_dev_info_get, |
e7eb703f | 1422 | .dev_status_get = hw_dev_status_get, |
ffedd0bf | 1423 | .hwcap_get_all = hw_hwcap_get_all, |
a9a245b4 | 1424 | .dev_config_set = hw_dev_config_set, |
6b3dfec8 UH |
1425 | .dev_acquisition_start = hw_dev_acquisition_start, |
1426 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
28a35d8a | 1427 | }; |