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Decoder for Xicor X2444M, nonvolatile static RAM.
[libsigrokdecode.git] / decoders / x2444m / pd.py
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1##
2## This file is part of the libsigrokdecode project.
3##
4## Copyright (C) 2018 Stefan Petersen <spe@ciellt.se>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, see <http://www.gnu.org/licenses/>.
18##
19
20import re
21import sigrokdecode as srd
22
23registers = {
24 0x80: ['WRDS', lambda _: ''],
25 0x81: ['STO', lambda _: ''],
26 0x82: ['SLEEP', lambda _: ''],
27 0x83: ['WRITE', lambda v: '0x%x' % v],
28 0x84: ['WREN', lambda _: ''],
29 0x85: ['RCL', lambda _: ''],
30 0x86: ['READ', lambda v: '0x%x' % v],
31 0x87: ['READ', lambda v: '0x%x' % v],
32}
33
34ann_write, ann_read = range(2)
35
36class Decoder(srd.Decoder):
37 api_version = 3
38 id = 'x2444m'
39 name = 'X2444M/P'
40 longname = 'Xicor X2444M/P'
41 desc = 'Xicor X2444M/P nonvolatile static RAM protocol.'
42 license = 'gplv2+'
43 inputs = ['spi']
44 outputs = ['x2444m']
45 annotations = (
46 ('write', 'Commands and data written to the device'),
47 ('read', 'Data read from the device'),
48 )
49 annotation_rows = (
50 ('data', 'Data', (ann_write, ann_read)),
51 )
52
53 def __init__(self):
54 self.reset()
55
56 def reset(self):
57 pass
58
59 def start(self):
60 self.out_ann = self.register(srd.OUTPUT_ANN)
61 self.cs_start = 0
62 self.cs_asserted = False
63 self.cmd_digit = 0
64
65 def putreadwrite(self, ss, es, reg, addr, value):
66 self.put(ss, es, self.out_ann,
67 [ann_write, ['%s: %s => 0x%4.4x' % (reg, addr, value)]])
68
69 def putcmd(self, ss, es, reg):
70 self.put(ss, es, self.out_ann, [ann_write, ['%s' % reg]])
71
72 def decode(self, ss, es, data):
73 ptype, mosi, miso = data
74
75 if ptype == 'DATA':
76 if not self.cs_asserted:
77 return
78
79 if self.cmd_digit == 0:
80 self.addr = mosi
81 self.addr_start = ss
82 elif self.cmd_digit > 0:
83 self.read_value = (self.read_value << 8) + miso
84 self.write_value = (self.write_value << 8) + mosi
85 self.cmd_digit += 1
86 elif ptype == 'CS-CHANGE':
87 self.cs_asserted = (miso == 1)
88 # When not asserted, CS has just changed from asserted to deasserted.
89 if not self.cs_asserted:
90 # Only one digit, simple command. Else read/write.
91 if self.cmd_digit == 1:
92 name, decoder = registers[self.addr & 0x87]
93 self.putcmd(self.addr_start, es, name)
94 elif self.cmd_digit > 1:
95 name, decoder = registers[self.addr & 0x87]
96 if name == 'READ':
97 value = self.read_value
98 elif name == 'WRITE':
99 value = self.write_value
100 else:
101 value = 0
102 self.putreadwrite(self.addr_start, es, name,
103 decoder((self.addr >> 3) & 0x0f), value)
104
105 if self.cs_asserted:
106 self.cs_start = ss
107 self.cmd_digit = 0
108 self.read_value = 0
109 self.write_value = 0