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1 | ## |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2016 Sean Burford <sburford@google.com> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
4539e9ca | 17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. |
1b1de569 SB |
18 | ## |
19 | ||
20 | import sigrokdecode as srd | |
21 | ||
22 | class Decoder(srd.Decoder): | |
23 | api_version = 2 | |
24 | id = 'wiegand' | |
25 | name = 'Wiegand' | |
26 | longname = 'Wiegand interface' | |
27 | desc = 'Wiegand interface for electronic entry systems.' | |
28 | license = 'gplv2+' | |
29 | inputs = ['logic'] | |
30 | outputs = ['wiegand'] | |
31 | channels = ( | |
32 | {'id': 'd0', 'name': 'D0', 'desc': 'Data 0 line'}, | |
33 | {'id': 'd1', 'name': 'D1', 'desc': 'Data 1 line'}, | |
34 | ) | |
35 | options = ( | |
36 | {'id': 'active', 'desc': 'Data lines active level', | |
37 | 'default': 'low', 'values': ('low', 'high')}, | |
38 | {'id': 'bitwidth_ms', 'desc': 'Single bit width in milliseconds', | |
366580f2 | 39 | 'default': 4, 'values': (1, 2, 4, 8, 16, 32)}, |
1b1de569 SB |
40 | ) |
41 | annotations = ( | |
42 | ('bits', 'Bits'), | |
43 | ('state', 'State'), | |
44 | ) | |
45 | annotation_rows = ( | |
46 | ('bits', 'Binary value', (0,)), | |
47 | ('state', 'Stream state', (1,)), | |
48 | ) | |
49 | ||
92b7b49f | 50 | def __init__(self): |
1b1de569 SB |
51 | self._samples_per_bit = 10 |
52 | ||
53 | self._d0_prev = None | |
54 | self._d1_prev = None | |
55 | ||
56 | self._state = None | |
5b0b88ce | 57 | self.ss_state = None |
1b1de569 SB |
58 | |
59 | self.ss_bit = None | |
60 | self.es_bit = None | |
61 | self._bit = None | |
62 | self._bits = [] | |
63 | ||
64 | def start(self): | |
65 | 'Register output types and verify user supplied decoder values.' | |
66 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
67 | self._active = self.options['active'] == 'high' and 1 or 0 | |
68 | self._inactive = 1 - self._active | |
69 | ||
70 | def metadata(self, key, value): | |
71 | 'Receive decoder metadata about the data stream.' | |
72 | if key == srd.SRD_CONF_SAMPLERATE: | |
73 | ms_per_sample = 1000 * (1.0 / value) | |
74 | ms_per_bit = float(self.options['bitwidth_ms']) | |
75 | self._samples_per_bit = int(max(1, int(ms_per_bit / ms_per_sample))) | |
76 | ||
77 | def _update_state(self, state, bit=None): | |
78 | 'Update state and bit values when they change.' | |
79 | if self._bit is not None: | |
80 | self._bits.append(self._bit) | |
81 | self.put(self.ss_bit, self.samplenum, self.out_ann, | |
82 | [0, [str(self._bit)]]) | |
83 | self._bit = bit | |
84 | self.ss_bit = self.samplenum | |
85 | if bit is not None: | |
86 | # Set a timeout so that the final bit ends. | |
87 | self.es_bit = self.samplenum + self._samples_per_bit | |
88 | else: | |
89 | self.es_bit = None | |
90 | ||
91 | if state != self._state: | |
92 | ann = None | |
93 | if self._state == 'data': | |
94 | accum_bits = ''.join(str(x) for x in self._bits) | |
95 | ann = [1, ['%d bits %s' % (len(self._bits), accum_bits), | |
96 | '%d bits' % len(self._bits)]] | |
97 | elif self._state == 'invalid': | |
98 | ann = [1, [self._state]] | |
99 | if ann: | |
5b0b88ce UH |
100 | self.put(self.ss_state, self.samplenum, self.out_ann, ann) |
101 | self.ss_state = self.samplenum | |
1b1de569 SB |
102 | self._state = state |
103 | self._bits = [] | |
104 | ||
105 | def decode(self, ss, es, data): | |
106 | for self.samplenum, (d0, d1) in data: | |
107 | if d0 == self._d0_prev and d1 == self._d1_prev: | |
108 | if self.es_bit and self.samplenum >= self.es_bit: | |
109 | if (d0, d1) == (self._inactive, self._inactive): | |
110 | self._update_state('idle') | |
111 | else: | |
112 | self._update_state('invalid') | |
113 | continue | |
114 | ||
115 | if self._state in (None, 'idle', 'data'): | |
116 | if (d0, d1) == (self._active, self._inactive): | |
117 | self._update_state('data', 0) | |
118 | elif (d0, d1) == (self._inactive, self._active): | |
119 | self._update_state('data', 1) | |
120 | elif (d0, d1) == (self._active, self._active): | |
121 | self._update_state('invalid') | |
122 | elif self._state == 'invalid': | |
123 | # Wait until we see an idle state before leaving invalid. | |
124 | # This prevents inverted lines from being misread. | |
125 | if (d0, d1) == (self._inactive, self._inactive): | |
126 | self._update_state('idle') | |
127 | ||
128 | self._d0_prev, self._d1_prev = d0, d1 | |
129 | ||
130 | def report(self): | |
131 | return '%s: %s D0 %d D1 %d (active on %d), %d samples per bit' % ( | |
132 | self.name, self._state, self._d0_prev, self._d1_prev, | |
133 | self._active, self._samples_per_bit) |