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1 | ## |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
4 | ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | # Texas Instruments TLC5620 protocol decoder | |
22 | ||
23 | import sigrokdecode as srd | |
24 | ||
25 | dacs = { | |
26 | 0: 'DACA', | |
27 | 1: 'DACB', | |
28 | 2: 'DACC', | |
29 | 3: 'DACD', | |
30 | } | |
31 | ||
32 | class Decoder(srd.Decoder): | |
33 | api_version = 1 | |
34 | id = 'tlc5620' | |
35 | name = 'TI TLC5620' | |
36 | longname = 'Texas Instruments TLC5620' | |
37 | desc = 'Texas Instruments TLC5620 8-bit quad DAC.' | |
38 | license = 'gplv2+' | |
39 | inputs = ['logic'] | |
40 | outputs = ['tlc5620'] | |
41 | probes = [ | |
42 | {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'}, | |
43 | {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'}, | |
44 | ] | |
45 | optional_probes = [ | |
46 | {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'}, | |
47 | {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'}, | |
48 | ] | |
49 | options = {} | |
50 | annotations = [ | |
51 | ['Text', 'Human-readable text'], | |
52 | ['Warnings', 'Human-readable warnings'], | |
53 | ] | |
54 | ||
55 | def __init__(self, **kwargs): | |
56 | self.state = 'IDLE' | |
57 | self.oldpins = None | |
58 | self.oldclk = None | |
59 | self.bits = [] | |
60 | self.ss_dac = self.es_dac = 0 | |
61 | self.ss_gain = self.es_gain = 0 | |
62 | self.ss_value = self.es_value = 0 | |
63 | ||
64 | def start(self, metadata): | |
65 | # self.out_proto = self.add(srd.OUTPUT_PROTO, 'tlc5620') | |
66 | self.out_ann = self.add(srd.OUTPUT_ANN, 'tlc5620') | |
67 | ||
68 | def report(self): | |
69 | pass | |
70 | ||
71 | def handle_11bits(self): | |
72 | s = "".join(str(i) for i in self.bits[:2]) | |
73 | self.put(self.ss_dac, self.es_dac, self.out_ann, | |
74 | [0, ['DAC select: %s' % dacs[int(s, 2)]]]) | |
75 | ||
76 | self.put(self.ss_gain, self.es_gain, self.out_ann, | |
77 | [0, ['Gain: x%d' % (1 + self.bits[2])]]) | |
78 | ||
79 | s = "".join(str(i) for i in self.bits[3:]) | |
80 | self.put(self.ss_value, self.es_value, self.out_ann, | |
81 | [0, ['DAC value: %d' % int(s, 2)]]) | |
82 | ||
83 | self.bits = [] | |
84 | ||
85 | def decode(self, ss, es, data): | |
86 | for (self.samplenum, pins) in data: | |
87 | ||
88 | # Ignore identical samples early on (for performance reasons). | |
89 | if self.oldpins == pins: | |
90 | continue | |
91 | self.oldpins, (clk, data, load, ldac) = pins, pins | |
92 | ||
93 | # DATA is shifted in the DAC on the falling CLK edge (MSB-first). | |
94 | # TODO: Handle various LOAD-/LDAC-controlled methods. | |
95 | if not (self.oldclk == 1 and clk == 0): | |
96 | self.oldclk = clk | |
97 | continue | |
98 | ||
99 | # The DAC has received a new bit, store it. | |
100 | self.bits.append(data) | |
101 | ||
102 | if self.state == 'IDLE': | |
103 | # Wait until we have read 11 bits, then parse them. | |
104 | l, s = len(self.bits), self.samplenum | |
105 | if l == 1: | |
106 | self.ss_dac = s | |
107 | elif l == 2: | |
108 | self.es_dac = self.ss_gain = s | |
109 | elif l == 3: | |
110 | self.es_gain = self.ss_value = s | |
111 | elif l == 11: | |
112 | self.es_value = s | |
113 | self.handle_11bits() | |
114 | else: | |
115 | raise Exception('Invalid state: %s' % self.state) | |
116 | ||
117 | self.oldclk = clk | |
118 |