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d4026957 | 1 | ## |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## Copyright (C) 2013 Matt Ranostay <mranostay@gmail.com> | |
6 | ## Copyright (C) 2014 alberink <alberink@stampfini.org> | |
7 | ## | |
8 | ## This program is free software; you can redistribute it and/or modify | |
9 | ## it under the terms of the GNU General Public License as published by | |
10 | ## the Free Software Foundation; either version 2 of the License, or | |
11 | ## (at your option) any later version. | |
12 | ## | |
13 | ## This program is distributed in the hope that it will be useful, | |
14 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ## GNU General Public License for more details. | |
17 | ## | |
18 | ## You should have received a copy of the GNU General Public License | |
4539e9ca | 19 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. |
d4026957 | 20 | ## |
21 | ||
22 | import sigrokdecode as srd | |
23 | ||
cc780304 UH |
24 | NUM_OUTPUT_CHANNELS = 8 |
25 | ||
26 | def logic_channels(num_channels): | |
27 | l = [] | |
28 | for i in range(num_channels): | |
460e6cfa | 29 | l.append(tuple(['p%d' % i, 'P-port input/output %d' % i])) |
cc780304 UH |
30 | return tuple(l) |
31 | ||
d4026957 | 32 | class Decoder(srd.Decoder): |
b197383c | 33 | api_version = 3 |
d4026957 | 34 | id = 'tca6408a' |
98c47d11 UH |
35 | name = 'TI TCA6408A' |
36 | longname = 'Texas Instruments TCA6408A' | |
d4026957 | 37 | desc = 'Texas Instruments TCA6408A 8-bit I²C I/O expander.' |
38 | license = 'gplv2+' | |
39 | inputs = ['i2c'] | |
6cbba91f | 40 | outputs = [] |
d6d8a8a4 | 41 | tags = ['Embedded/industrial', 'IC'] |
d4026957 | 42 | annotations = ( |
43 | ('register', 'Register type'), | |
44 | ('value', 'Register value'), | |
e144452b | 45 | ('warning', 'Warning'), |
d4026957 | 46 | ) |
cc780304 | 47 | logic_output_channels = logic_channels(NUM_OUTPUT_CHANNELS) |
d4026957 | 48 | annotation_rows = ( |
49 | ('regs', 'Registers', (0, 1)), | |
50 | ('warnings', 'Warnings', (2,)), | |
51 | ) | |
52 | ||
92b7b49f | 53 | def __init__(self): |
10aeb8ea GS |
54 | self.reset() |
55 | ||
56 | def reset(self): | |
d4026957 | 57 | self.state = 'IDLE' |
58 | self.chip = -1 | |
9b6c0354 SA |
59 | |
60 | self.logic_es = 1 | |
61 | self.logic_data = [] | |
62 | for i in range(NUM_OUTPUT_CHANNELS): | |
63 | self.logic_data.append(bytes([1])) | |
d4026957 | 64 | |
65 | def start(self): | |
66 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
cc780304 | 67 | self.out_logic = self.register(srd.OUTPUT_LOGIC) |
d4026957 | 68 | |
69 | def putx(self, data): | |
70 | self.put(self.ss, self.es, self.out_ann, data) | |
71 | ||
9b6c0354 SA |
72 | def put_logic_states(self): |
73 | if (self.es > self.logic_es): | |
74 | for i in range(NUM_OUTPUT_CHANNELS): | |
75 | self.put(self.logic_es, self.es, self.out_logic, [i, self.logic_data[i]]) | |
76 | self.logic_es = self.es | |
cc780304 | 77 | |
d4026957 | 78 | def handle_reg_0x00(self, b): |
79 | self.putx([1, ['State of inputs: %02X' % b]]) | |
cc780304 | 80 | # TODO |
d4026957 | 81 | |
82 | def handle_reg_0x01(self, b): | |
cc780304 | 83 | self.putx([1, ['Outputs set: %02X' % b]]) |
cc780304 UH |
84 | for i in range(NUM_OUTPUT_CHANNELS): |
85 | bit = (b & (1 << i)) != 0 | |
9b6c0354 | 86 | self.logic_data[i] = bytes([bit]) |
d4026957 | 87 | |
88 | def handle_reg_0x02(self, b): | |
89 | self.putx([1, ['Polarity inverted: %02X' % b]]) | |
90 | ||
91 | def handle_reg_0x03(self, b): | |
92 | self.putx([1, ['Configuration: %02X' % b]]) | |
93 | ||
94 | def handle_write_reg(self, b): | |
95 | if b == 0: | |
96 | self.putx([0, ['Input port', 'In', 'I']]) | |
97 | elif b == 1: | |
98 | self.putx([0, ['Output port', 'Out', 'O']]) | |
99 | elif b == 2: | |
100 | self.putx([0, ['Polarity inversion register', 'Pol', 'P']]) | |
101 | elif b == 3: | |
102 | self.putx([0, ['Configuration register', 'Conf', 'C']]) | |
103 | ||
104 | def check_correct_chip(self, addr): | |
105 | if addr not in (0x20, 0x21): | |
106 | self.putx([2, ['Warning: I²C slave 0x%02X not a TCA6408A ' | |
107 | 'compatible chip.' % addr]]) | |
108 | self.state = 'IDLE' | |
109 | ||
110 | def decode(self, ss, es, data): | |
111 | cmd, databyte = data | |
112 | ||
113 | # Store the start/end samples of this I²C packet. | |
114 | self.ss, self.es = ss, es | |
115 | ||
9b6c0354 SA |
116 | self.put_logic_states() |
117 | ||
d4026957 | 118 | # State machine. |
119 | if self.state == 'IDLE': | |
120 | # Wait for an I²C START condition. | |
121 | if cmd != 'START': | |
122 | return | |
123 | self.state = 'GET SLAVE ADDR' | |
d4026957 | 124 | elif self.state == 'GET SLAVE ADDR': |
18101a31 | 125 | self.chip = databyte |
d4026957 | 126 | self.state = 'GET REG ADDR' |
127 | elif self.state == 'GET REG ADDR': | |
128 | # Wait for a data write (master selects the slave register). | |
129 | if cmd in ('ADDRESS READ', 'ADDRESS WRITE'): | |
130 | self.check_correct_chip(databyte) | |
131 | if cmd != 'DATA WRITE': | |
132 | return | |
133 | self.reg = databyte | |
134 | self.handle_write_reg(self.reg) | |
135 | self.state = 'WRITE IO REGS' | |
136 | elif self.state == 'WRITE IO REGS': | |
137 | # If we see a Repeated Start here, the master wants to read. | |
138 | if cmd == 'START REPEAT': | |
139 | self.state = 'READ IO REGS' | |
140 | return | |
141 | # Otherwise: Get data bytes until a STOP condition occurs. | |
142 | if cmd == 'DATA WRITE': | |
143 | handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg) | |
144 | handle_reg(databyte) | |
145 | elif cmd == 'STOP': | |
146 | self.state = 'IDLE' | |
147 | self.chip = -1 | |
148 | elif self.state == 'READ IO REGS': | |
149 | # Wait for an address read operation. | |
150 | if cmd == 'ADDRESS READ': | |
151 | self.state = 'READ IO REGS2' | |
152 | self.chip = databyte | |
153 | return | |
154 | elif self.state == 'READ IO REGS2': | |
155 | if cmd == 'DATA READ': | |
156 | handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg) | |
157 | handle_reg(databyte) | |
158 | elif cmd == 'STOP': | |
159 | self.state = 'IDLE' |