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2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2019-2020 Benjamin Vernoux <bvernoux@gmail.com> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | ## | |
19 | ## v0.1 - 17 September 2019 B.VERNOUX using ST25R3916 Datasheet DS12484 Rev 1 (January 2019) | |
20 | ## v0.2 - 28 April 2020 B.VERNOUX using ST25R3916 Datasheet DS12484 Rev 2 (December 2019) https://www.st.com/resource/en/datasheet/st25r3916.pdf | |
21 | ## v0.3 - 17 June 2020 B.VERNOUX using ST25R3916 Datasheet DS12484 Rev 3 (04 June 2020) https://www.st.com/resource/en/datasheet/st25r3916.pdf | |
22 | ||
23 | ## ST25R3916 Datasheet DS12484 Rev 3 (04 June 2020) §4.4 Direct commands | |
24 | dir_cmd = { | |
25 | # addr: 'name' | |
26 | # Set Default | |
27 | 0xC0: 'SET_DEFAULT', | |
28 | 0xC1: 'SET_DEFAULT', | |
29 | # Stop All Activities | |
30 | 0xC2: 'STOP', | |
31 | 0xC3: 'STOP', | |
32 | # Transmit With CRC | |
33 | 0xC4: 'TXCRC', | |
34 | # Transmit Without CRC | |
35 | 0xC5: 'TXNOCRC', | |
36 | # Transmit REQA | |
37 | 0xC6: 'TXREQA', | |
38 | # Transmit WUPA | |
39 | 0xC7: 'TXWUPA', | |
40 | # NFC Initial Field ON | |
41 | 0xC8: 'NFCINITFON', | |
42 | # NFC Response Field ON | |
43 | 0xC9: 'NFCRESFON', | |
44 | # Go to Sense (Idle) | |
45 | 0xCD: 'GOIDLE', | |
46 | # Go to Sleep (Halt) | |
47 | 0xCE: 'GOHALT', | |
48 | # Mask Receive Data / Stops receivers and RX decoders | |
49 | 0xD0: 'STOPRX', | |
50 | # Unmask Receive Data / Starts receivers and RX decoders | |
51 | 0xD1: 'STARRX', | |
52 | # Change AM Modulation state | |
53 | 0xD2: 'SETAMSTATE', | |
54 | # Measure Amplitude | |
55 | 0xD3: 'MAMP', | |
56 | # Reset RX Gain | |
57 | 0xD5: 'RSTRXGAIN', | |
58 | # Adjust Regulators | |
59 | 0xD6: 'ADJREG', | |
60 | # Calibrate Driver Timing | |
61 | 0xD8: 'CALDRVTIM', | |
62 | # Measure Phase | |
63 | 0xD9: 'MPHASE', | |
64 | # Clear RSSI | |
65 | 0xDA: 'CLRRSSI', | |
66 | # Clear FIFO | |
67 | 0xDB: 'CLRFIFO', | |
68 | # Enter Transparent Mode | |
69 | 0xDC: 'TRMODE', | |
70 | # Calibrate Capacitive Sensor | |
71 | 0xDD: 'CALCAPA', | |
72 | # Measure Capacitance | |
73 | 0xDE: 'MCAPA', | |
74 | # Measure Power Supply | |
75 | 0xDF: 'MPOWER', | |
76 | # Start General Purpose Timer | |
77 | 0xE0: 'STARGPTIM', | |
78 | # Start Wake-up Timer | |
79 | 0xE1: 'STARWTIM', | |
80 | # Start Mask-receive Timer | |
81 | 0xE2: 'STARMSKTIM', | |
82 | # Start No-response Timer | |
83 | 0xE3: 'STARNRESPTIM', | |
84 | # Start PPON2 Timer | |
85 | 0xE4: 'STARPPON2TIM', | |
86 | # Stop No-response Timer | |
87 | 0xE8: 'STOPNRESTIM', | |
88 | # RFU / Not Used | |
89 | 0xFA: 'RFU', | |
90 | # Register Space-B Access | |
91 | 0xFB: 'REGSPACEB', | |
92 | # Register Test access | |
93 | 0xFC: 'TESTACCESS' | |
94 | # Other codes => RFU / Not Used | |
95 | } | |
96 | ||
97 | ## ST25R3916 Datasheet DS12484 Rev 2 (December 2019) §4.5 Registers Table 17. List of registers - Space A | |
98 | ## ST25R3916 Datasheet DS12484 Rev 2 (December 2019) §4.3.3 Serial peripheral interface (SPI) Table 11. SPI operation modes | |
99 | regsSpaceA = { | |
100 | # addr: 'name' | |
101 | # §4.5 Registers Table 17. List of registers - Space A | |
102 | # IO configuration | |
103 | 0x00: 'IOCFG1', | |
104 | 0x01: 'IOCFG2', | |
105 | # Operation control and mode definition | |
106 | 0x02: 'OPCTRL', | |
107 | 0x03: 'MODEDEF', | |
108 | 0x04: 'BITRATE', | |
109 | # Protocol configuration | |
110 | 0x05: 'TYPEA', | |
111 | 0x06: 'TYPEB', | |
112 | 0x07: 'TYPEBF', | |
113 | 0x08: 'NFCIP1', | |
114 | 0x09: 'STREAM', | |
115 | 0x0A: 'AUX', | |
116 | # Receiver configuration | |
117 | 0x0B: 'RXCFG1', | |
118 | 0x0C: 'RXCFG2', | |
119 | 0x0D: 'RXCFG3', | |
120 | 0x0E: 'RXCFG4', | |
121 | # Timer definition | |
122 | 0x0F: 'MSKRXTIM', | |
123 | 0x10: 'NRESPTIM1', | |
124 | 0x11: 'NRESPTIM2', | |
125 | 0x12: 'TIMEMV', | |
126 | 0x13: 'GPTIM1', | |
127 | 0x14: 'GPTIM2', | |
128 | 0x15: 'PPON2', | |
129 | # Interrupt and associated reporting | |
130 | 0x16: 'MSKMAINIRQ', | |
131 | 0x17: 'MSKTIMNFCIRQ', | |
132 | 0x18: 'MSKERRWAKEIRQ', | |
133 | 0x19: 'TARGIRQ', | |
134 | 0x1A: 'MAINIRQ', | |
135 | 0x1B: 'TIMNFCIRQ', | |
136 | 0x1C: 'ERRWAKEIRQ', | |
137 | 0x1D: 'TARGIRQ', | |
138 | 0x1E: 'FIFOSTAT1', | |
139 | 0x1F: 'FIFOSTAT2', | |
140 | 0x20: 'COLLDISP', | |
141 | 0x21: 'TARGDISP', | |
142 | # Definition of number of transmitted bytes | |
143 | 0x22: 'NBTXB1', | |
144 | 0x23: 'NBTXB2', | |
145 | 0x24: 'BITRATEDET', | |
146 | # A/D converter output | |
147 | 0x25: 'ADCONVOUT', | |
148 | # Antenna calibration | |
149 | 0x26: 'ANTTUNECTRL1', | |
150 | 0x27: 'ANTTUNECTRL2', | |
151 | # Antenna driver and modulation | |
152 | 0x28: 'TXDRV', | |
153 | 0x29: 'TARGMOD', | |
154 | # External field detector threshold | |
155 | 0x2A: 'EXTFIELDON', | |
156 | 0x2B: 'EXTFIELDOFF', | |
157 | # Regulator | |
158 | 0x2C: 'REGVDDCTRL', | |
159 | # Receiver state display | |
160 | 0x2D: 'RSSIDISP', | |
161 | 0x2E: 'GAINSTATE', | |
162 | # Capacitive sensor | |
163 | 0x2F: 'CAPACTRL', | |
164 | 0x30: 'CAPADISP', | |
165 | # Auxiliary display | |
166 | 0x31: 'AUXDISP', | |
167 | # Wake-up | |
168 | 0x32: 'WAKETIMCTRL', | |
169 | 0x33: 'AMPCFG', | |
170 | 0x34: 'AMPREF', | |
171 | 0x35: 'AMPAAVGDISP', | |
172 | 0x36: 'AMPDISP', | |
173 | 0x37: 'PHASECFG', | |
174 | 0x38: 'PHASEREF', | |
175 | 0x39: 'PHASEAAVGDISP', | |
176 | 0x3A: 'PHASEDISP', | |
177 | 0x3B: 'CAPACFG', | |
178 | 0x3C: 'CAPAREF', | |
179 | 0x3D: 'CAPAAAVGDISP', | |
180 | 0x3E: 'CAPADISP', | |
181 | # IC identity | |
182 | 0x3F: 'ICIDENT', | |
183 | ## ST25R3916 Datasheet DS12484 Rev 2 (December 2019) §4.3.3 Serial peripheral interface (SPI) Table 11. SPI operation modes | |
184 | 0xA0: 'PT_memLoadA', | |
185 | 0xA8: 'PT_memLoadF', | |
186 | 0xAC: 'PT_memLoadTSN', | |
187 | 0xBF: 'PT_memRead' | |
188 | } | |
189 | ||
190 | ## ST25R3916 Datasheet DS12484 Rev 2 (December 2019) §4.5 Registers Table 18. List of registers - Space B | |
191 | regsSpaceB = { | |
192 | # addr: 'name' | |
193 | # §4.5 Registers Table 18. List of registers - Space B | |
194 | # Protocol configuration | |
195 | 0x05: 'EMDSUPPRCONF', | |
196 | 0x06: 'SUBCSTARTIM', | |
197 | # Receiver configuration | |
198 | 0x0B: 'P2PRXCONF', | |
199 | 0x0C: 'CORRCONF1', | |
200 | 0x0D: 'CORRCONF2', | |
201 | # Timer definition | |
202 | 0x0F: 'SQUELSHTIM', | |
203 | 0x15: 'NFCGUARDTIM', | |
204 | # Antenna driver and modulation | |
205 | 0x28: 'AUXMODSET', | |
206 | 0x29: 'TXDRVTIM', | |
207 | # External field detector threshold | |
208 | 0x2A: 'RESAMMODE', | |
209 | 0x2B: 'TXDRVTIMDISP', | |
210 | # Regulator | |
211 | 0x2C: 'REGDISP', | |
212 | # Protection | |
213 | 0x30: 'OSHOOTCONF1', | |
214 | 0x31: 'OSHOOTCONF2', | |
215 | 0x32: 'USHOOTCONF1', | |
216 | 0x33: 'USHOOTCONF2' | |
217 | } | |
218 | ||
219 | ## ST25R3916 Datasheet DS12484 Rev 2 (December 2019) §4.4.17 Test access | |
220 | regsTest = { | |
221 | # addr: 'name' | |
222 | # §4.4.17 Test access (Typo in datasheet it is not register 0x00 but 0x01) | |
223 | 0x01: 'ANTSTOBS' | |
224 | } | |
225 | ||
226 | ## Optional TODO add important status bit fields / ANN_STATUS | |
227 | ## Interrupt and associated reporting => Registers Space A from Address (hex) 0x16 to 0x21 | |
228 | ## §4.5.58 RSSI display register | |
229 | ## §4.5.59 Gain reduction state register | |
230 | ## ... | |
231 |