]>
Commit | Line | Data |
---|---|---|
6eb87578 GM |
1 | ## |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
d6bace96 | 5 | ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de> |
6eb87578 GM |
6 | ## |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
18 | ## along with this program; if not, write to the Free Software | |
19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | ## | |
ad2dc0de | 21 | |
677d597b | 22 | import sigrokdecode as srd |
67e847fd | 23 | |
238b4080 UH |
24 | # Chip-select options |
25 | ACTIVE_LOW = 0 | |
26 | ACTIVE_HIGH = 1 | |
27 | ||
28 | # Clock polarity options | |
29 | CPOL_0 = 0 # Clock is low when inactive | |
30 | CPOL_1 = 1 # Clock is high when inactive | |
31 | ||
32 | # Clock phase options | |
acba4869 UH |
33 | CPHA_0 = 0 # Data is valid on the leading clock edge |
34 | CPHA_1 = 1 # Data is valid on the trailing clock edge | |
238b4080 UH |
35 | |
36 | # Bit order options | |
37 | MSB_FIRST = 0 | |
0c3089c1 | 38 | LSB_FIRST = 1 |
238b4080 | 39 | |
8a7ce2a3 | 40 | # Key: (CPOL, CPHA). Value: SPI mode. |
c94c8c91 UH |
41 | spi_mode = { |
42 | (0, 0): 0, # Mode 0 | |
43 | (0, 1): 1, # Mode 1 | |
44 | (1, 0): 2, # Mode 2 | |
45 | (1, 1): 3, # Mode 3 | |
46 | } | |
47 | ||
d6bace96 UH |
48 | # Annotation formats |
49 | ANN_HEX = 0 | |
50 | ||
677d597b | 51 | class Decoder(srd.Decoder): |
a2c2afd9 | 52 | api_version = 1 |
67e847fd | 53 | id = 'spi' |
2b7d0e2b | 54 | name = 'SPI' |
3d3da57d | 55 | longname = 'Serial Peripheral Interface' |
9a12a6e7 | 56 | desc = '...desc...' |
6eb87578 | 57 | longdesc = '...longdesc...' |
6eb87578 GM |
58 | license = 'gplv2+' |
59 | inputs = ['logic'] | |
60 | outputs = ['spi'] | |
6b5b91d2 | 61 | probes = [ |
4e570fa9 UH |
62 | {'id': 'miso', 'name': 'MISO', |
63 | 'desc': 'SPI MISO line (Master in, slave out)'}, | |
decde15e UH |
64 | {'id': 'mosi', 'name': 'MOSI', |
65 | 'desc': 'SPI MOSI line (Master out, slave in)'}, | |
6b5b91d2 | 66 | {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, |
4e570fa9 | 67 | {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'}, |
6b5b91d2 | 68 | ] |
decde15e | 69 | extra_probes = [] # TODO |
238b4080 | 70 | options = { |
acba4869 | 71 | 'cs_polarity': ['CS# polarity', ACTIVE_LOW], |
c94c8c91 UH |
72 | 'cpol': ['Clock polarity', CPOL_0], |
73 | 'cpha': ['Clock phase', CPHA_0], | |
74 | 'bitorder': ['Bit order within the SPI data', MSB_FIRST], | |
75 | 'wordsize': ['Word size of SPI data', 8], # 1-64? | |
238b4080 | 76 | } |
b1bb5eed | 77 | annotations = [ |
d6bace96 | 78 | ['Hex', 'SPI data bytes in hex format'], |
b1bb5eed | 79 | ] |
6eb87578 | 80 | |
3643fc3f | 81 | def __init__(self): |
c66baa8c | 82 | self.oldsck = 1 |
a10bfc48 | 83 | self.bitcount = 0 |
4917bb31 | 84 | self.mosidata = 0 |
d6bace96 | 85 | self.misodata = 0 |
6eb87578 | 86 | self.bytesreceived = 0 |
d6bace96 | 87 | self.samplenum = -1 |
01329e88 | 88 | self.cs_was_deasserted_during_data_word = 0 |
6eb87578 | 89 | |
3643fc3f | 90 | def start(self, metadata): |
d6bace96 | 91 | self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') |
56202222 | 92 | self.out_ann = self.add(srd.OUTPUT_ANN, 'spi') |
3643fc3f | 93 | |
6eb87578 | 94 | def report(self): |
e100d51e | 95 | return 'SPI: %d bytes received' % self.bytesreceived |
6eb87578 | 96 | |
2b9837d9 | 97 | def decode(self, ss, es, data): |
decde15e UH |
98 | # TODO: Either MISO or MOSI could be optional. CS# is optional. |
99 | for (samplenum, (miso, mosi, sck, cs)) in data: | |
6eb87578 | 100 | |
d6bace96 UH |
101 | self.samplenum += 1 # FIXME |
102 | ||
c94c8c91 | 103 | # Ignore sample if the clock pin hasn't changed. |
6eb87578 GM |
104 | if sck == self.oldsck: |
105 | continue | |
c94c8c91 | 106 | |
6eb87578 | 107 | self.oldsck = sck |
c94c8c91 UH |
108 | |
109 | # Sample data on rising/falling clock edge (depends on mode). | |
8a7ce2a3 | 110 | mode = spi_mode[self.options['cpol'], self.options['cpha']] |
c94c8c91 UH |
111 | if mode == 0 and sck == 0: # Sample on rising clock edge |
112 | continue | |
113 | elif mode == 1 and sck == 1: # Sample on falling clock edge | |
114 | continue | |
115 | elif mode == 2 and sck == 1: # Sample on falling clock edge | |
116 | continue | |
117 | elif mode == 3 and sck == 0: # Sample on rising clock edge | |
118 | continue | |
6eb87578 | 119 | |
d6bace96 | 120 | # If this is the first bit, save its sample number. |
a10bfc48 | 121 | if self.bitcount == 0: |
d6bace96 | 122 | self.start_sample = samplenum |
8a7ce2a3 UH |
123 | active_low = (self.options['cs_polarity'] == ACTIVE_LOW) |
124 | deasserted = cs if active_low else not cs | |
acba4869 | 125 | if deasserted: |
01329e88 | 126 | self.cs_was_deasserted_during_data_word = 1 |
b1bb5eed | 127 | |
fd4aa8aa UH |
128 | ws = self.options['wordsize'] |
129 | ||
1ea831e9 | 130 | # Receive MOSI bit into our shift register. |
8a7ce2a3 | 131 | if self.options['bitorder'] == MSB_FIRST: |
fd4aa8aa | 132 | self.mosidata |= mosi << (ws - 1 - self.bitcount) |
1ea831e9 UH |
133 | else: |
134 | self.mosidata |= mosi << self.bitcount | |
135 | ||
136 | # Receive MISO bit into our shift register. | |
8a7ce2a3 | 137 | if self.options['bitorder'] == MSB_FIRST: |
fd4aa8aa | 138 | self.misodata |= miso << (ws - 1 - self.bitcount) |
1ea831e9 UH |
139 | else: |
140 | self.misodata |= miso << self.bitcount | |
b1bb5eed | 141 | |
a10bfc48 | 142 | self.bitcount += 1 |
b1bb5eed | 143 | |
fd4aa8aa UH |
144 | # Continue to receive if not enough bits were received, yet. |
145 | if self.bitcount != ws: | |
6eb87578 | 146 | continue |
b1bb5eed | 147 | |
d6bace96 UH |
148 | self.put(self.start_sample, self.samplenum, self.out_proto, |
149 | ['data', self.mosidata, self.misodata]) | |
150 | self.put(self.start_sample, self.samplenum, self.out_ann, | |
151 | [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata, | |
152 | self.misodata)]]) | |
b1bb5eed | 153 | |
01329e88 UH |
154 | if self.cs_was_deasserted_during_data_word: |
155 | self.put(self.start_sample, self.samplenum, self.out_ann, | |
acba4869 UH |
156 | [ANN_HEX, ['WARNING: CS# was deasserted during this ' |
157 | 'SPI data byte!']]) | |
01329e88 | 158 | |
b1bb5eed | 159 | # Reset decoder state. |
4917bb31 | 160 | self.mosidata = 0 |
d6bace96 | 161 | self.misodata = 0 |
a10bfc48 | 162 | self.bitcount = 0 |
b1bb5eed UH |
163 | |
164 | # Keep stats for summary. | |
6eb87578 | 165 | self.bytesreceived += 1 |
ad2dc0de | 166 |