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1 | ## |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2018 Max Weller | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | ## | |
19 | ||
20 | import re | |
21 | import sigrokdecode as srd | |
22 | ||
23 | ann_cmdbit, ann_databit, ann_cmd, ann_data, ann_warning = range(5) | |
24 | ||
25 | class Decoder(srd.Decoder): | |
26 | api_version = 3 | |
27 | id = 'sda2506' | |
28 | name = 'SDA2506' | |
29 | longname = 'Siemens SDA 2506-5' | |
c14ef8e3 | 30 | desc = 'Serial nonvolatile 1-Kbit EEPROM.' |
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31 | license = 'gplv2+' |
32 | inputs = ['logic'] | |
6cbba91f | 33 | outputs = [] |
d6d8a8a4 | 34 | tags = ['IC', 'Memory'] |
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35 | channels = ( |
36 | {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'}, | |
37 | {'id': 'd', 'name': 'DATA', 'desc': 'Data'}, | |
38 | {'id': 'ce', 'name': 'CE#', 'desc': 'Chip-enable'}, | |
39 | ) | |
40 | annotations = ( | |
41 | ('cmdbit', 'Command bit'), | |
42 | ('databit', 'Data bit'), | |
43 | ('cmd', 'Command'), | |
44 | ('data', 'Data byte'), | |
45 | ('warnings', 'Human-readable warnings'), | |
46 | ) | |
47 | annotation_rows = ( | |
48 | ('bits', 'Bits', (ann_cmdbit, ann_databit)), | |
49 | ('commands', 'Commands', (ann_cmd,)), | |
50 | ('data', 'Data', (ann_data,)), | |
51 | ('warnings', 'Warnings', (ann_warning,)), | |
52 | ) | |
53 | ||
54 | def __init__(self): | |
55 | self.samplerate = None | |
56 | self.reset() | |
57 | ||
58 | def reset(self): | |
59 | self.cmdbits = [] | |
60 | self.databits = [] | |
61 | ||
62 | def metadata(self, key, value): | |
63 | if key == srd.SRD_CONF_SAMPLERATE: | |
64 | self.samplerate = value | |
65 | ||
66 | def start(self): | |
67 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
68 | ||
69 | def putbit(self, ss, es, typ, value): | |
70 | self.put(ss, es, self.out_ann, [typ, ['%s' % (value)]]) | |
71 | ||
72 | def putdata(self, ss, es): | |
73 | value = 0 | |
74 | for i in range(8): | |
75 | value = (value << 1) | self.databits[i] | |
76 | self.put(ss, es, self.out_ann, [ann_data, ['%02X' % (value)]]) | |
77 | ||
78 | def decode_bits(self, offset, width): | |
79 | out = 0 | |
80 | for i in range(width): | |
81 | out = (out << 1) | self.cmdbits[offset + i][0] | |
82 | return (out, self.cmdbits[offset + width - 1][1], self.cmdbits[offset][2]) | |
83 | ||
84 | def decode_field(self, name, offset, width): | |
85 | val, ss, es = self.decode_bits(offset, width) | |
86 | self.put(ss, es, self.out_ann, [ann_data, ['%s: %02X' % (name, val)]]) | |
87 | return val | |
88 | ||
89 | def decode(self): | |
90 | while True: | |
91 | # Wait for CLK edge or CE edge. | |
92 | clk, d, ce = self.wait([{0: 'e'}, {2: 'e'}]) | |
93 | ||
94 | if self.matched[0] and ce == 1 and clk == 1: | |
95 | # Rising clk edge and command mode. | |
96 | bitstart = self.samplenum | |
97 | self.wait({0: 'f'}) | |
98 | self.cmdbits = [(d, bitstart, self.samplenum)] + self.cmdbits | |
99 | if len(self.cmdbits) > 24: | |
100 | self.cmdbits = self.cmdbits[0:24] | |
101 | self.putbit(bitstart, self.samplenum, ann_cmdbit, d) | |
102 | elif self.matched[0] and ce == 0 and clk == 0: | |
103 | # Falling clk edge and data mode. | |
104 | bitstart = self.samplenum | |
105 | clk, d, ce = self.wait([{'skip': int(2.5 * (1e6 / self.samplerate))}, {0: 'r'}, {2: 'e'}]) # Wait 25 us for data ready. | |
106 | if self.matched == (True, False, False): | |
107 | self.wait([{0: 'r'}, {2: 'e'}]) | |
108 | if len(self.databits) == 0: | |
109 | self.datastart = bitstart | |
110 | self.databits = [d] + self.databits | |
111 | self.putbit(bitstart, self.samplenum, ann_databit, d) | |
112 | if len(self.databits) == 8: | |
113 | self.putdata(self.datastart, self.samplenum) | |
114 | self.databits = [] | |
115 | elif self.matched[1] and ce == 0: | |
116 | # Chip enable edge. | |
117 | try: | |
118 | self.decode_field('addr', 1, 7) | |
119 | self.decode_field('CB', 0, 1) | |
120 | if self.cmdbits[0][0] == 0: | |
121 | # Beginning read command. | |
122 | self.decode_field('read', 1, 7) | |
123 | self.put(self.cmdbits[7][1], self.samplenum, | |
124 | self.out_ann, [ann_cmd, ['read' ]]) | |
125 | elif d == 0: | |
126 | # Beginning write command. | |
127 | self.decode_field('data', 8, 8) | |
128 | addr, ss, es = self.decode_bits(1, 7) | |
129 | data, ss, es = self.decode_bits(8, 8) | |
130 | cmdstart = self.samplenum | |
131 | self.wait({2: 'r'}) | |
132 | self.put(cmdstart, self.samplenum, self.out_ann, | |
133 | [ann_cmd, ['Write to %02X: %02X' % (addr, data)]]) | |
134 | else: | |
135 | # Beginning erase command. | |
136 | val, ss, es = self.decode_bits(1, 7) | |
137 | cmdstart = self.samplenum | |
138 | self.wait({2: 'r'}) | |
139 | self.put(cmdstart, self.samplenum, self.out_ann, | |
140 | [ann_cmd, ['Erase: %02X' % (val)]]) | |
141 | self.databits = [] | |
142 | except Exception as ex: | |
143 | self.reset() |