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702fa251 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
702fa251 | 3 | ## |
e20f455c | 4 | ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de> |
702fa251 UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
4539e9ca | 17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. |
702fa251 | 18 | ## |
702fa251 UH |
19 | |
20 | import sigrokdecode as srd | |
21 | ||
21cda951 UH |
22 | class SamplerateError(Exception): |
23 | pass | |
24 | ||
702fa251 | 25 | class Decoder(srd.Decoder): |
64d87119 | 26 | api_version = 3 |
702fa251 UH |
27 | id = 'can' |
28 | name = 'CAN' | |
9e1437a0 | 29 | longname = 'Controller Area Network' |
702fa251 UH |
30 | desc = 'Field bus protocol for distributed realtime control.' |
31 | license = 'gplv2+' | |
32 | inputs = ['logic'] | |
6cbba91f | 33 | outputs = [] |
d6d8a8a4 | 34 | tags = ['Automotive'] |
6a15597a | 35 | channels = ( |
702fa251 | 36 | {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'}, |
da9bcbd9 | 37 | ) |
84c1c0b5 | 38 | options = ( |
b0918d40 UH |
39 | {'id': 'bitrate', 'desc': 'Bitrate (bits/s)', 'default': 1000000}, |
40 | {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0}, | |
84c1c0b5 | 41 | ) |
da9bcbd9 BV |
42 | annotations = ( |
43 | ('data', 'CAN payload data'), | |
44 | ('sof', 'Start of frame'), | |
45 | ('eof', 'End of frame'), | |
46 | ('id', 'Identifier'), | |
47 | ('ext-id', 'Extended identifier'), | |
48 | ('full-id', 'Full identifier'), | |
49 | ('ide', 'Identifier extension bit'), | |
50 | ('reserved-bit', 'Reserved bit 0 and 1'), | |
51 | ('rtr', 'Remote transmission request'), | |
52 | ('srr', 'Substitute remote request'), | |
53 | ('dlc', 'Data length count'), | |
54 | ('crc-sequence', 'CRC sequence'), | |
55 | ('crc-delimiter', 'CRC delimiter'), | |
56 | ('ack-slot', 'ACK slot'), | |
57 | ('ack-delimiter', 'ACK delimiter'), | |
58 | ('stuff-bit', 'Stuff bit'), | |
59 | ('warnings', 'Human-readable warnings'), | |
544038d9 | 60 | ('bit', 'Bit'), |
d4a28d0f UH |
61 | ) |
62 | annotation_rows = ( | |
544038d9 | 63 | ('bits', 'Bits', (15, 17)), |
2fac4493 UH |
64 | ('fields', 'Fields', tuple(range(15))), |
65 | ('warnings', 'Warnings', (16,)), | |
da9bcbd9 | 66 | ) |
702fa251 | 67 | |
92b7b49f | 68 | def __init__(self): |
10aeb8ea GS |
69 | self.reset() |
70 | ||
71 | def reset(self): | |
f372d597 | 72 | self.samplerate = None |
702fa251 UH |
73 | self.reset_variables() |
74 | ||
f372d597 | 75 | def start(self): |
be465111 | 76 | self.out_ann = self.register(srd.OUTPUT_ANN) |
702fa251 | 77 | |
f372d597 BV |
78 | def metadata(self, key, value): |
79 | if key == srd.SRD_CONF_SAMPLERATE: | |
80 | self.samplerate = value | |
81 | self.bit_width = float(self.samplerate) / float(self.options['bitrate']) | |
300f9194 | 82 | self.sample_point = (self.bit_width / 100.0) * self.options['sample_point'] |
702fa251 | 83 | |
4b1813b4 UH |
84 | # Generic helper for CAN bit annotations. |
85 | def putg(self, ss, es, data): | |
300f9194 | 86 | left, right = int(self.sample_point), int(self.bit_width - self.sample_point) |
4b1813b4 UH |
87 | self.put(ss - left, es + right, self.out_ann, data) |
88 | ||
89 | # Single-CAN-bit annotation using the current samplenum. | |
e20f455c | 90 | def putx(self, data): |
4b1813b4 UH |
91 | self.putg(self.samplenum, self.samplenum, data) |
92 | ||
93 | # Single-CAN-bit annotation using the samplenum of CAN bit 12. | |
94 | def put12(self, data): | |
95 | self.putg(self.ss_bit12, self.ss_bit12, data) | |
96 | ||
97 | # Multi-CAN-bit annotation from self.ss_block to current samplenum. | |
98 | def putb(self, data): | |
99 | self.putg(self.ss_block, self.samplenum, data) | |
e20f455c | 100 | |
702fa251 UH |
101 | def reset_variables(self): |
102 | self.state = 'IDLE' | |
103 | self.sof = self.frame_type = self.dlc = None | |
104 | self.rawbits = [] # All bits, including stuff bits | |
105 | self.bits = [] # Only actual CAN frame bits (no stuff bits) | |
106 | self.curbit = 0 # Current bit of CAN frame (bit 0 == SOF) | |
107 | self.last_databit = 999 # Positive value that bitnum+x will never match | |
4b1813b4 UH |
108 | self.ss_block = None |
109 | self.ss_bit12 = None | |
110 | self.ss_databytebits = [] | |
702fa251 | 111 | |
45a50880 GS |
112 | # Poor man's clock synchronization. Use signal edges which change to |
113 | # dominant state in rather simple ways. This naive approach is neither | |
114 | # aware of the SYNC phase's width nor the specific location of the edge, | |
115 | # but improves the decoder's reliability when the input signal's bitrate | |
116 | # does not exactly match the nominal rate. | |
117 | def dom_edge_seen(self, force = False): | |
118 | self.dom_edge_snum = self.samplenum | |
119 | self.dom_edge_bcount = self.curbit | |
120 | ||
121 | def bit_sampled(self): | |
122 | # EMPTY | |
123 | pass | |
124 | ||
64d87119 GS |
125 | # Determine the position of the next desired bit's sample point. |
126 | def get_sample_point(self, bitnum): | |
45a50880 GS |
127 | samplenum = self.dom_edge_snum |
128 | samplenum += int(self.bit_width * (bitnum - self.dom_edge_bcount)) | |
129 | samplenum += int(self.sample_point) | |
300f9194 | 130 | return samplenum |
702fa251 UH |
131 | |
132 | def is_stuff_bit(self): | |
133 | # CAN uses NRZ encoding and bit stuffing. | |
134 | # After 5 identical bits, a stuff bit of opposite value is added. | |
a0128522 | 135 | # But not in the CRC delimiter, ACK, and end of frame fields. |
cffb6592 | 136 | if len(self.bits) > self.last_databit + 17: |
a0128522 | 137 | return False |
702fa251 UH |
138 | last_6_bits = self.rawbits[-6:] |
139 | if last_6_bits not in ([0, 0, 0, 0, 0, 1], [1, 1, 1, 1, 1, 0]): | |
140 | return False | |
141 | ||
142 | # Stuff bit. Keep it in self.rawbits, but drop it from self.bits. | |
702fa251 UH |
143 | self.bits.pop() # Drop last bit. |
144 | return True | |
145 | ||
146 | def is_valid_crc(self, crc_bits): | |
147 | return True # TODO | |
148 | ||
149 | def decode_error_frame(self, bits): | |
150 | pass # TODO | |
151 | ||
152 | def decode_overload_frame(self, bits): | |
153 | pass # TODO | |
154 | ||
155 | # Both standard and extended frames end with CRC, CRC delimiter, ACK, | |
156 | # ACK delimiter, and EOF fields. Handle them in a common function. | |
157 | # Returns True if the frame ended (EOF), False otherwise. | |
158 | def decode_frame_end(self, can_rx, bitnum): | |
159 | ||
4b1813b4 UH |
160 | # Remember start of CRC sequence (see below). |
161 | if bitnum == (self.last_databit + 1): | |
162 | self.ss_block = self.samplenum | |
163 | ||
702fa251 | 164 | # CRC sequence (15 bits) |
4b1813b4 | 165 | elif bitnum == (self.last_databit + 15): |
702fa251 UH |
166 | x = self.last_databit + 1 |
167 | crc_bits = self.bits[x:x + 15 + 1] | |
168 | self.crc = int(''.join(str(d) for d in crc_bits), 2) | |
74c9bb3c UH |
169 | self.putb([11, ['CRC sequence: 0x%04x' % self.crc, |
170 | 'CRC: 0x%04x' % self.crc, 'CRC']]) | |
702fa251 | 171 | if not self.is_valid_crc(crc_bits): |
74c9bb3c | 172 | self.putb([16, ['CRC is invalid']]) |
702fa251 UH |
173 | |
174 | # CRC delimiter bit (recessive) | |
175 | elif bitnum == (self.last_databit + 16): | |
74c9bb3c UH |
176 | self.putx([12, ['CRC delimiter: %d' % can_rx, |
177 | 'CRC d: %d' % can_rx, 'CRC d']]) | |
2fac4493 UH |
178 | if can_rx != 1: |
179 | self.putx([16, ['CRC delimiter must be a recessive bit']]) | |
702fa251 UH |
180 | |
181 | # ACK slot bit (dominant: ACK, recessive: NACK) | |
182 | elif bitnum == (self.last_databit + 17): | |
183 | ack = 'ACK' if can_rx == 0 else 'NACK' | |
74c9bb3c | 184 | self.putx([13, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']]) |
702fa251 UH |
185 | |
186 | # ACK delimiter bit (recessive) | |
187 | elif bitnum == (self.last_databit + 18): | |
74c9bb3c UH |
188 | self.putx([14, ['ACK delimiter: %d' % can_rx, |
189 | 'ACK d: %d' % can_rx, 'ACK d']]) | |
2fac4493 UH |
190 | if can_rx != 1: |
191 | self.putx([16, ['ACK delimiter must be a recessive bit']]) | |
702fa251 | 192 | |
4b1813b4 UH |
193 | # Remember start of EOF (see below). |
194 | elif bitnum == (self.last_databit + 19): | |
195 | self.ss_block = self.samplenum | |
196 | ||
702fa251 UH |
197 | # End of frame (EOF), 7 recessive bits |
198 | elif bitnum == (self.last_databit + 25): | |
74c9bb3c | 199 | self.putb([2, ['End of frame', 'EOF', 'E']]) |
2fac4493 UH |
200 | if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]: |
201 | self.putb([16, ['End of frame (EOF) must be 7 recessive bits']]) | |
702fa251 UH |
202 | self.reset_variables() |
203 | return True | |
204 | ||
205 | return False | |
206 | ||
207 | # Returns True if the frame ended (EOF), False otherwise. | |
208 | def decode_standard_frame(self, can_rx, bitnum): | |
209 | ||
210 | # Bit 14: RB0 (reserved bit) | |
211 | # Has to be sent dominant, but receivers should accept recessive too. | |
212 | if bitnum == 14: | |
74c9bb3c | 213 | self.putx([7, ['Reserved bit 0: %d' % can_rx, |
534ae912 | 214 | 'RB0: %d' % can_rx, 'RB0']]) |
702fa251 UH |
215 | |
216 | # Bit 12: Remote transmission request (RTR) bit | |
217 | # Data frame: dominant, remote frame: recessive | |
218 | # Remote frames do not contain a data field. | |
219 | rtr = 'remote' if self.bits[12] == 1 else 'data' | |
74c9bb3c | 220 | self.put12([8, ['Remote transmission request: %s frame' % rtr, |
534ae912 | 221 | 'RTR: %s frame' % rtr, 'RTR']]) |
4b1813b4 UH |
222 | |
223 | # Remember start of DLC (see below). | |
224 | elif bitnum == 15: | |
225 | self.ss_block = self.samplenum | |
702fa251 UH |
226 | |
227 | # Bits 15-18: Data length code (DLC), in number of bytes (0-8). | |
228 | elif bitnum == 18: | |
229 | self.dlc = int(''.join(str(d) for d in self.bits[15:18 + 1]), 2) | |
74c9bb3c UH |
230 | self.putb([10, ['Data length code: %d' % self.dlc, |
231 | 'DLC: %d' % self.dlc, 'DLC']]) | |
702fa251 | 232 | self.last_databit = 18 + (self.dlc * 8) |
2fac4493 UH |
233 | if self.dlc > 8: |
234 | self.putb([16, ['Data length code (DLC) > 8 is not allowed']]) | |
702fa251 | 235 | |
4b1813b4 UH |
236 | # Remember all databyte bits, except the very last one. |
237 | elif bitnum in range(19, self.last_databit): | |
238 | self.ss_databytebits.append(self.samplenum) | |
239 | ||
702fa251 UH |
240 | # Bits 19-X: Data field (0-8 bytes, depending on DLC) |
241 | # The bits within a data byte are transferred MSB-first. | |
242 | elif bitnum == self.last_databit: | |
4b1813b4 | 243 | self.ss_databytebits.append(self.samplenum) # Last databyte bit. |
702fa251 UH |
244 | for i in range(self.dlc): |
245 | x = 18 + (8 * i) + 1 | |
246 | b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) | |
4b1813b4 UH |
247 | ss = self.ss_databytebits[i * 8] |
248 | es = self.ss_databytebits[((i + 1) * 8) - 1] | |
534ae912 UH |
249 | self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b), |
250 | 'DB %d: 0x%02x' % (i, b), 'DB']]) | |
4b1813b4 | 251 | self.ss_databytebits = [] |
702fa251 UH |
252 | |
253 | elif bitnum > self.last_databit: | |
254 | return self.decode_frame_end(can_rx, bitnum) | |
255 | ||
256 | return False | |
257 | ||
258 | # Returns True if the frame ended (EOF), False otherwise. | |
259 | def decode_extended_frame(self, can_rx, bitnum): | |
260 | ||
4b1813b4 UH |
261 | # Remember start of EID (see below). |
262 | if bitnum == 14: | |
263 | self.ss_block = self.samplenum | |
264 | ||
702fa251 | 265 | # Bits 14-31: Extended identifier (EID[17..0]) |
4b1813b4 | 266 | elif bitnum == 31: |
702fa251 | 267 | self.eid = int(''.join(str(d) for d in self.bits[14:]), 2) |
534ae912 | 268 | s = '%d (0x%x)' % (self.eid, self.eid) |
74c9bb3c | 269 | self.putb([4, ['Extended Identifier: %s' % s, |
534ae912 | 270 | 'Extended ID: %s' % s, 'Extended ID', 'EID']]) |
702fa251 UH |
271 | |
272 | self.fullid = self.id << 18 | self.eid | |
534ae912 | 273 | s = '%d (0x%x)' % (self.fullid, self.fullid) |
74c9bb3c | 274 | self.putb([5, ['Full Identifier: %s' % s, 'Full ID: %s' % s, |
534ae912 | 275 | 'Full ID', 'FID']]) |
702fa251 UH |
276 | |
277 | # Bit 12: Substitute remote request (SRR) bit | |
74c9bb3c | 278 | self.put12([9, ['Substitute remote request: %d' % self.bits[12], |
534ae912 | 279 | 'SRR: %d' % self.bits[12], 'SRR']]) |
702fa251 UH |
280 | |
281 | # Bit 32: Remote transmission request (RTR) bit | |
282 | # Data frame: dominant, remote frame: recessive | |
283 | # Remote frames do not contain a data field. | |
284 | if bitnum == 32: | |
285 | rtr = 'remote' if can_rx == 1 else 'data' | |
74c9bb3c | 286 | self.putx([8, ['Remote transmission request: %s frame' % rtr, |
534ae912 | 287 | 'RTR: %s frame' % rtr, 'RTR']]) |
702fa251 UH |
288 | |
289 | # Bit 33: RB1 (reserved bit) | |
290 | elif bitnum == 33: | |
74c9bb3c | 291 | self.putx([7, ['Reserved bit 1: %d' % can_rx, |
534ae912 | 292 | 'RB1: %d' % can_rx, 'RB1']]) |
702fa251 UH |
293 | |
294 | # Bit 34: RB0 (reserved bit) | |
295 | elif bitnum == 34: | |
74c9bb3c | 296 | self.putx([7, ['Reserved bit 0: %d' % can_rx, |
534ae912 | 297 | 'RB0: %d' % can_rx, 'RB0']]) |
702fa251 | 298 | |
4b1813b4 UH |
299 | # Remember start of DLC (see below). |
300 | elif bitnum == 35: | |
301 | self.ss_block = self.samplenum | |
302 | ||
702fa251 UH |
303 | # Bits 35-38: Data length code (DLC), in number of bytes (0-8). |
304 | elif bitnum == 38: | |
305 | self.dlc = int(''.join(str(d) for d in self.bits[35:38 + 1]), 2) | |
74c9bb3c UH |
306 | self.putb([10, ['Data length code: %d' % self.dlc, |
307 | 'DLC: %d' % self.dlc, 'DLC']]) | |
702fa251 UH |
308 | self.last_databit = 38 + (self.dlc * 8) |
309 | ||
4b1813b4 UH |
310 | # Remember all databyte bits, except the very last one. |
311 | elif bitnum in range(39, self.last_databit): | |
312 | self.ss_databytebits.append(self.samplenum) | |
313 | ||
702fa251 UH |
314 | # Bits 39-X: Data field (0-8 bytes, depending on DLC) |
315 | # The bits within a data byte are transferred MSB-first. | |
316 | elif bitnum == self.last_databit: | |
4b1813b4 | 317 | self.ss_databytebits.append(self.samplenum) # Last databyte bit. |
702fa251 UH |
318 | for i in range(self.dlc): |
319 | x = 38 + (8 * i) + 1 | |
320 | b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) | |
4b1813b4 UH |
321 | ss = self.ss_databytebits[i * 8] |
322 | es = self.ss_databytebits[((i + 1) * 8) - 1] | |
534ae912 UH |
323 | self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b), |
324 | 'DB %d: 0x%02x' % (i, b), 'DB']]) | |
4b1813b4 | 325 | self.ss_databytebits = [] |
702fa251 UH |
326 | |
327 | elif bitnum > self.last_databit: | |
328 | return self.decode_frame_end(can_rx, bitnum) | |
329 | ||
330 | return False | |
331 | ||
332 | def handle_bit(self, can_rx): | |
333 | self.rawbits.append(can_rx) | |
334 | self.bits.append(can_rx) | |
335 | ||
336 | # Get the index of the current CAN frame bit (without stuff bits). | |
337 | bitnum = len(self.bits) - 1 | |
338 | ||
702fa251 UH |
339 | # If this is a stuff bit, remove it from self.bits and ignore it. |
340 | if self.is_stuff_bit(): | |
544038d9 | 341 | self.putx([15, [str(can_rx)]]) |
702fa251 UH |
342 | self.curbit += 1 # Increase self.curbit (bitnum is not affected). |
343 | return | |
544038d9 UH |
344 | else: |
345 | self.putx([17, [str(can_rx)]]) | |
702fa251 UH |
346 | |
347 | # Bit 0: Start of frame (SOF) bit | |
348 | if bitnum == 0: | |
2fac4493 UH |
349 | self.putx([1, ['Start of frame', 'SOF', 'S']]) |
350 | if can_rx != 0: | |
74c9bb3c | 351 | self.putx([16, ['Start of frame (SOF) must be a dominant bit']]) |
702fa251 | 352 | |
4b1813b4 UH |
353 | # Remember start of ID (see below). |
354 | elif bitnum == 1: | |
355 | self.ss_block = self.samplenum | |
356 | ||
702fa251 UH |
357 | # Bits 1-11: Identifier (ID[10..0]) |
358 | # The bits ID[10..4] must NOT be all recessive. | |
359 | elif bitnum == 11: | |
360 | self.id = int(''.join(str(d) for d in self.bits[1:]), 2) | |
534ae912 | 361 | s = '%d (0x%x)' % (self.id, self.id), |
74c9bb3c | 362 | self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']]) |
2fac4493 UH |
363 | if (self.id & 0x7f0) == 0x7f0: |
364 | self.putb([16, ['Identifier bits 10..4 must not be all recessive']]) | |
702fa251 UH |
365 | |
366 | # RTR or SRR bit, depending on frame type (gets handled later). | |
367 | elif bitnum == 12: | |
4b1813b4 UH |
368 | # self.putx([0, ['RTR/SRR: %d' % can_rx]]) # Debug only. |
369 | self.ss_bit12 = self.samplenum | |
702fa251 UH |
370 | |
371 | # Bit 13: Identifier extension (IDE) bit | |
372 | # Standard frame: dominant, extended frame: recessive | |
373 | elif bitnum == 13: | |
374 | ide = self.frame_type = 'standard' if can_rx == 0 else 'extended' | |
74c9bb3c | 375 | self.putx([6, ['Identifier extension bit: %s frame' % ide, |
534ae912 | 376 | 'IDE: %s frame' % ide, 'IDE']]) |
702fa251 UH |
377 | |
378 | # Bits 14-X: Frame-type dependent, passed to the resp. handlers. | |
379 | elif bitnum >= 14: | |
380 | if self.frame_type == 'standard': | |
381 | done = self.decode_standard_frame(can_rx, bitnum) | |
382 | else: | |
383 | done = self.decode_extended_frame(can_rx, bitnum) | |
384 | ||
385 | # The handlers return True if a frame ended (EOF). | |
386 | if done: | |
387 | return | |
388 | ||
389 | # After a frame there are 3 intermission bits (recessive). | |
390 | # After these bits, the bus is considered free. | |
391 | ||
392 | self.curbit += 1 | |
393 | ||
64d87119 | 394 | def decode(self): |
21cda951 UH |
395 | if not self.samplerate: |
396 | raise SamplerateError('Cannot decode without samplerate.') | |
702fa251 | 397 | |
64d87119 | 398 | while True: |
702fa251 UH |
399 | # State machine. |
400 | if self.state == 'IDLE': | |
401 | # Wait for a dominant state (logic 0) on the bus. | |
64d87119 | 402 | (can_rx,) = self.wait({0: 'l'}) |
702fa251 | 403 | self.sof = self.samplenum |
45a50880 | 404 | self.dom_edge_seen(force = True) |
702fa251 UH |
405 | self.state = 'GET BITS' |
406 | elif self.state == 'GET BITS': | |
407 | # Wait until we're in the correct bit/sampling position. | |
64d87119 | 408 | pos = self.get_sample_point(self.curbit) |
45a50880 GS |
409 | (can_rx,) = self.wait([{'skip': pos - self.samplenum}, {0: 'f'}]) |
410 | if self.matched[1]: | |
411 | self.dom_edge_seen() | |
412 | if self.matched[0]: | |
413 | self.handle_bit(can_rx) | |
414 | self.bit_sampled() |