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702fa251 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
702fa251 | 3 | ## |
e20f455c | 4 | ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de> |
702fa251 UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
4539e9ca | 17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. |
702fa251 | 18 | ## |
702fa251 UH |
19 | |
20 | import sigrokdecode as srd | |
21 | ||
21cda951 UH |
22 | class SamplerateError(Exception): |
23 | pass | |
24 | ||
702fa251 | 25 | class Decoder(srd.Decoder): |
64d87119 | 26 | api_version = 3 |
702fa251 UH |
27 | id = 'can' |
28 | name = 'CAN' | |
9e1437a0 | 29 | longname = 'Controller Area Network' |
702fa251 UH |
30 | desc = 'Field bus protocol for distributed realtime control.' |
31 | license = 'gplv2+' | |
32 | inputs = ['logic'] | |
33 | outputs = ['can'] | |
6a15597a | 34 | channels = ( |
702fa251 | 35 | {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'}, |
da9bcbd9 | 36 | ) |
84c1c0b5 | 37 | options = ( |
b0918d40 UH |
38 | {'id': 'bitrate', 'desc': 'Bitrate (bits/s)', 'default': 1000000}, |
39 | {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0}, | |
84c1c0b5 | 40 | ) |
da9bcbd9 BV |
41 | annotations = ( |
42 | ('data', 'CAN payload data'), | |
43 | ('sof', 'Start of frame'), | |
44 | ('eof', 'End of frame'), | |
45 | ('id', 'Identifier'), | |
46 | ('ext-id', 'Extended identifier'), | |
47 | ('full-id', 'Full identifier'), | |
48 | ('ide', 'Identifier extension bit'), | |
49 | ('reserved-bit', 'Reserved bit 0 and 1'), | |
50 | ('rtr', 'Remote transmission request'), | |
51 | ('srr', 'Substitute remote request'), | |
52 | ('dlc', 'Data length count'), | |
53 | ('crc-sequence', 'CRC sequence'), | |
54 | ('crc-delimiter', 'CRC delimiter'), | |
55 | ('ack-slot', 'ACK slot'), | |
56 | ('ack-delimiter', 'ACK delimiter'), | |
57 | ('stuff-bit', 'Stuff bit'), | |
58 | ('warnings', 'Human-readable warnings'), | |
544038d9 | 59 | ('bit', 'Bit'), |
d4a28d0f UH |
60 | ) |
61 | annotation_rows = ( | |
544038d9 | 62 | ('bits', 'Bits', (15, 17)), |
2fac4493 UH |
63 | ('fields', 'Fields', tuple(range(15))), |
64 | ('warnings', 'Warnings', (16,)), | |
da9bcbd9 | 65 | ) |
702fa251 | 66 | |
92b7b49f | 67 | def __init__(self): |
10aeb8ea GS |
68 | self.reset() |
69 | ||
70 | def reset(self): | |
f372d597 | 71 | self.samplerate = None |
702fa251 UH |
72 | self.reset_variables() |
73 | ||
f372d597 | 74 | def start(self): |
be465111 | 75 | self.out_ann = self.register(srd.OUTPUT_ANN) |
702fa251 | 76 | |
f372d597 BV |
77 | def metadata(self, key, value): |
78 | if key == srd.SRD_CONF_SAMPLERATE: | |
79 | self.samplerate = value | |
80 | self.bit_width = float(self.samplerate) / float(self.options['bitrate']) | |
300f9194 | 81 | self.sample_point = (self.bit_width / 100.0) * self.options['sample_point'] |
702fa251 | 82 | |
4b1813b4 UH |
83 | # Generic helper for CAN bit annotations. |
84 | def putg(self, ss, es, data): | |
300f9194 | 85 | left, right = int(self.sample_point), int(self.bit_width - self.sample_point) |
4b1813b4 UH |
86 | self.put(ss - left, es + right, self.out_ann, data) |
87 | ||
88 | # Single-CAN-bit annotation using the current samplenum. | |
e20f455c | 89 | def putx(self, data): |
4b1813b4 UH |
90 | self.putg(self.samplenum, self.samplenum, data) |
91 | ||
92 | # Single-CAN-bit annotation using the samplenum of CAN bit 12. | |
93 | def put12(self, data): | |
94 | self.putg(self.ss_bit12, self.ss_bit12, data) | |
95 | ||
96 | # Multi-CAN-bit annotation from self.ss_block to current samplenum. | |
97 | def putb(self, data): | |
98 | self.putg(self.ss_block, self.samplenum, data) | |
e20f455c | 99 | |
702fa251 UH |
100 | def reset_variables(self): |
101 | self.state = 'IDLE' | |
102 | self.sof = self.frame_type = self.dlc = None | |
103 | self.rawbits = [] # All bits, including stuff bits | |
104 | self.bits = [] # Only actual CAN frame bits (no stuff bits) | |
105 | self.curbit = 0 # Current bit of CAN frame (bit 0 == SOF) | |
106 | self.last_databit = 999 # Positive value that bitnum+x will never match | |
4b1813b4 UH |
107 | self.ss_block = None |
108 | self.ss_bit12 = None | |
109 | self.ss_databytebits = [] | |
702fa251 | 110 | |
45a50880 GS |
111 | # Poor man's clock synchronization. Use signal edges which change to |
112 | # dominant state in rather simple ways. This naive approach is neither | |
113 | # aware of the SYNC phase's width nor the specific location of the edge, | |
114 | # but improves the decoder's reliability when the input signal's bitrate | |
115 | # does not exactly match the nominal rate. | |
116 | def dom_edge_seen(self, force = False): | |
117 | self.dom_edge_snum = self.samplenum | |
118 | self.dom_edge_bcount = self.curbit | |
119 | ||
120 | def bit_sampled(self): | |
121 | # EMPTY | |
122 | pass | |
123 | ||
64d87119 GS |
124 | # Determine the position of the next desired bit's sample point. |
125 | def get_sample_point(self, bitnum): | |
45a50880 GS |
126 | samplenum = self.dom_edge_snum |
127 | samplenum += int(self.bit_width * (bitnum - self.dom_edge_bcount)) | |
128 | samplenum += int(self.sample_point) | |
300f9194 | 129 | return samplenum |
702fa251 UH |
130 | |
131 | def is_stuff_bit(self): | |
132 | # CAN uses NRZ encoding and bit stuffing. | |
133 | # After 5 identical bits, a stuff bit of opposite value is added. | |
a0128522 | 134 | # But not in the CRC delimiter, ACK, and end of frame fields. |
cffb6592 | 135 | if len(self.bits) > self.last_databit + 17: |
a0128522 | 136 | return False |
702fa251 UH |
137 | last_6_bits = self.rawbits[-6:] |
138 | if last_6_bits not in ([0, 0, 0, 0, 0, 1], [1, 1, 1, 1, 1, 0]): | |
139 | return False | |
140 | ||
141 | # Stuff bit. Keep it in self.rawbits, but drop it from self.bits. | |
702fa251 UH |
142 | self.bits.pop() # Drop last bit. |
143 | return True | |
144 | ||
145 | def is_valid_crc(self, crc_bits): | |
146 | return True # TODO | |
147 | ||
148 | def decode_error_frame(self, bits): | |
149 | pass # TODO | |
150 | ||
151 | def decode_overload_frame(self, bits): | |
152 | pass # TODO | |
153 | ||
154 | # Both standard and extended frames end with CRC, CRC delimiter, ACK, | |
155 | # ACK delimiter, and EOF fields. Handle them in a common function. | |
156 | # Returns True if the frame ended (EOF), False otherwise. | |
157 | def decode_frame_end(self, can_rx, bitnum): | |
158 | ||
4b1813b4 UH |
159 | # Remember start of CRC sequence (see below). |
160 | if bitnum == (self.last_databit + 1): | |
161 | self.ss_block = self.samplenum | |
162 | ||
702fa251 | 163 | # CRC sequence (15 bits) |
4b1813b4 | 164 | elif bitnum == (self.last_databit + 15): |
702fa251 UH |
165 | x = self.last_databit + 1 |
166 | crc_bits = self.bits[x:x + 15 + 1] | |
167 | self.crc = int(''.join(str(d) for d in crc_bits), 2) | |
74c9bb3c UH |
168 | self.putb([11, ['CRC sequence: 0x%04x' % self.crc, |
169 | 'CRC: 0x%04x' % self.crc, 'CRC']]) | |
702fa251 | 170 | if not self.is_valid_crc(crc_bits): |
74c9bb3c | 171 | self.putb([16, ['CRC is invalid']]) |
702fa251 UH |
172 | |
173 | # CRC delimiter bit (recessive) | |
174 | elif bitnum == (self.last_databit + 16): | |
74c9bb3c UH |
175 | self.putx([12, ['CRC delimiter: %d' % can_rx, |
176 | 'CRC d: %d' % can_rx, 'CRC d']]) | |
2fac4493 UH |
177 | if can_rx != 1: |
178 | self.putx([16, ['CRC delimiter must be a recessive bit']]) | |
702fa251 UH |
179 | |
180 | # ACK slot bit (dominant: ACK, recessive: NACK) | |
181 | elif bitnum == (self.last_databit + 17): | |
182 | ack = 'ACK' if can_rx == 0 else 'NACK' | |
74c9bb3c | 183 | self.putx([13, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']]) |
702fa251 UH |
184 | |
185 | # ACK delimiter bit (recessive) | |
186 | elif bitnum == (self.last_databit + 18): | |
74c9bb3c UH |
187 | self.putx([14, ['ACK delimiter: %d' % can_rx, |
188 | 'ACK d: %d' % can_rx, 'ACK d']]) | |
2fac4493 UH |
189 | if can_rx != 1: |
190 | self.putx([16, ['ACK delimiter must be a recessive bit']]) | |
702fa251 | 191 | |
4b1813b4 UH |
192 | # Remember start of EOF (see below). |
193 | elif bitnum == (self.last_databit + 19): | |
194 | self.ss_block = self.samplenum | |
195 | ||
702fa251 UH |
196 | # End of frame (EOF), 7 recessive bits |
197 | elif bitnum == (self.last_databit + 25): | |
74c9bb3c | 198 | self.putb([2, ['End of frame', 'EOF', 'E']]) |
2fac4493 UH |
199 | if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]: |
200 | self.putb([16, ['End of frame (EOF) must be 7 recessive bits']]) | |
702fa251 UH |
201 | self.reset_variables() |
202 | return True | |
203 | ||
204 | return False | |
205 | ||
206 | # Returns True if the frame ended (EOF), False otherwise. | |
207 | def decode_standard_frame(self, can_rx, bitnum): | |
208 | ||
209 | # Bit 14: RB0 (reserved bit) | |
210 | # Has to be sent dominant, but receivers should accept recessive too. | |
211 | if bitnum == 14: | |
74c9bb3c | 212 | self.putx([7, ['Reserved bit 0: %d' % can_rx, |
534ae912 | 213 | 'RB0: %d' % can_rx, 'RB0']]) |
702fa251 UH |
214 | |
215 | # Bit 12: Remote transmission request (RTR) bit | |
216 | # Data frame: dominant, remote frame: recessive | |
217 | # Remote frames do not contain a data field. | |
218 | rtr = 'remote' if self.bits[12] == 1 else 'data' | |
74c9bb3c | 219 | self.put12([8, ['Remote transmission request: %s frame' % rtr, |
534ae912 | 220 | 'RTR: %s frame' % rtr, 'RTR']]) |
4b1813b4 UH |
221 | |
222 | # Remember start of DLC (see below). | |
223 | elif bitnum == 15: | |
224 | self.ss_block = self.samplenum | |
702fa251 UH |
225 | |
226 | # Bits 15-18: Data length code (DLC), in number of bytes (0-8). | |
227 | elif bitnum == 18: | |
228 | self.dlc = int(''.join(str(d) for d in self.bits[15:18 + 1]), 2) | |
74c9bb3c UH |
229 | self.putb([10, ['Data length code: %d' % self.dlc, |
230 | 'DLC: %d' % self.dlc, 'DLC']]) | |
702fa251 | 231 | self.last_databit = 18 + (self.dlc * 8) |
2fac4493 UH |
232 | if self.dlc > 8: |
233 | self.putb([16, ['Data length code (DLC) > 8 is not allowed']]) | |
702fa251 | 234 | |
4b1813b4 UH |
235 | # Remember all databyte bits, except the very last one. |
236 | elif bitnum in range(19, self.last_databit): | |
237 | self.ss_databytebits.append(self.samplenum) | |
238 | ||
702fa251 UH |
239 | # Bits 19-X: Data field (0-8 bytes, depending on DLC) |
240 | # The bits within a data byte are transferred MSB-first. | |
241 | elif bitnum == self.last_databit: | |
4b1813b4 | 242 | self.ss_databytebits.append(self.samplenum) # Last databyte bit. |
702fa251 UH |
243 | for i in range(self.dlc): |
244 | x = 18 + (8 * i) + 1 | |
245 | b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) | |
4b1813b4 UH |
246 | ss = self.ss_databytebits[i * 8] |
247 | es = self.ss_databytebits[((i + 1) * 8) - 1] | |
534ae912 UH |
248 | self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b), |
249 | 'DB %d: 0x%02x' % (i, b), 'DB']]) | |
4b1813b4 | 250 | self.ss_databytebits = [] |
702fa251 UH |
251 | |
252 | elif bitnum > self.last_databit: | |
253 | return self.decode_frame_end(can_rx, bitnum) | |
254 | ||
255 | return False | |
256 | ||
257 | # Returns True if the frame ended (EOF), False otherwise. | |
258 | def decode_extended_frame(self, can_rx, bitnum): | |
259 | ||
4b1813b4 UH |
260 | # Remember start of EID (see below). |
261 | if bitnum == 14: | |
262 | self.ss_block = self.samplenum | |
263 | ||
702fa251 | 264 | # Bits 14-31: Extended identifier (EID[17..0]) |
4b1813b4 | 265 | elif bitnum == 31: |
702fa251 | 266 | self.eid = int(''.join(str(d) for d in self.bits[14:]), 2) |
534ae912 | 267 | s = '%d (0x%x)' % (self.eid, self.eid) |
74c9bb3c | 268 | self.putb([4, ['Extended Identifier: %s' % s, |
534ae912 | 269 | 'Extended ID: %s' % s, 'Extended ID', 'EID']]) |
702fa251 UH |
270 | |
271 | self.fullid = self.id << 18 | self.eid | |
534ae912 | 272 | s = '%d (0x%x)' % (self.fullid, self.fullid) |
74c9bb3c | 273 | self.putb([5, ['Full Identifier: %s' % s, 'Full ID: %s' % s, |
534ae912 | 274 | 'Full ID', 'FID']]) |
702fa251 UH |
275 | |
276 | # Bit 12: Substitute remote request (SRR) bit | |
74c9bb3c | 277 | self.put12([9, ['Substitute remote request: %d' % self.bits[12], |
534ae912 | 278 | 'SRR: %d' % self.bits[12], 'SRR']]) |
702fa251 UH |
279 | |
280 | # Bit 32: Remote transmission request (RTR) bit | |
281 | # Data frame: dominant, remote frame: recessive | |
282 | # Remote frames do not contain a data field. | |
283 | if bitnum == 32: | |
284 | rtr = 'remote' if can_rx == 1 else 'data' | |
74c9bb3c | 285 | self.putx([8, ['Remote transmission request: %s frame' % rtr, |
534ae912 | 286 | 'RTR: %s frame' % rtr, 'RTR']]) |
702fa251 UH |
287 | |
288 | # Bit 33: RB1 (reserved bit) | |
289 | elif bitnum == 33: | |
74c9bb3c | 290 | self.putx([7, ['Reserved bit 1: %d' % can_rx, |
534ae912 | 291 | 'RB1: %d' % can_rx, 'RB1']]) |
702fa251 UH |
292 | |
293 | # Bit 34: RB0 (reserved bit) | |
294 | elif bitnum == 34: | |
74c9bb3c | 295 | self.putx([7, ['Reserved bit 0: %d' % can_rx, |
534ae912 | 296 | 'RB0: %d' % can_rx, 'RB0']]) |
702fa251 | 297 | |
4b1813b4 UH |
298 | # Remember start of DLC (see below). |
299 | elif bitnum == 35: | |
300 | self.ss_block = self.samplenum | |
301 | ||
702fa251 UH |
302 | # Bits 35-38: Data length code (DLC), in number of bytes (0-8). |
303 | elif bitnum == 38: | |
304 | self.dlc = int(''.join(str(d) for d in self.bits[35:38 + 1]), 2) | |
74c9bb3c UH |
305 | self.putb([10, ['Data length code: %d' % self.dlc, |
306 | 'DLC: %d' % self.dlc, 'DLC']]) | |
702fa251 UH |
307 | self.last_databit = 38 + (self.dlc * 8) |
308 | ||
4b1813b4 UH |
309 | # Remember all databyte bits, except the very last one. |
310 | elif bitnum in range(39, self.last_databit): | |
311 | self.ss_databytebits.append(self.samplenum) | |
312 | ||
702fa251 UH |
313 | # Bits 39-X: Data field (0-8 bytes, depending on DLC) |
314 | # The bits within a data byte are transferred MSB-first. | |
315 | elif bitnum == self.last_databit: | |
4b1813b4 | 316 | self.ss_databytebits.append(self.samplenum) # Last databyte bit. |
702fa251 UH |
317 | for i in range(self.dlc): |
318 | x = 38 + (8 * i) + 1 | |
319 | b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) | |
4b1813b4 UH |
320 | ss = self.ss_databytebits[i * 8] |
321 | es = self.ss_databytebits[((i + 1) * 8) - 1] | |
534ae912 UH |
322 | self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b), |
323 | 'DB %d: 0x%02x' % (i, b), 'DB']]) | |
4b1813b4 | 324 | self.ss_databytebits = [] |
702fa251 UH |
325 | |
326 | elif bitnum > self.last_databit: | |
327 | return self.decode_frame_end(can_rx, bitnum) | |
328 | ||
329 | return False | |
330 | ||
331 | def handle_bit(self, can_rx): | |
332 | self.rawbits.append(can_rx) | |
333 | self.bits.append(can_rx) | |
334 | ||
335 | # Get the index of the current CAN frame bit (without stuff bits). | |
336 | bitnum = len(self.bits) - 1 | |
337 | ||
702fa251 UH |
338 | # If this is a stuff bit, remove it from self.bits and ignore it. |
339 | if self.is_stuff_bit(): | |
544038d9 | 340 | self.putx([15, [str(can_rx)]]) |
702fa251 UH |
341 | self.curbit += 1 # Increase self.curbit (bitnum is not affected). |
342 | return | |
544038d9 UH |
343 | else: |
344 | self.putx([17, [str(can_rx)]]) | |
702fa251 UH |
345 | |
346 | # Bit 0: Start of frame (SOF) bit | |
347 | if bitnum == 0: | |
2fac4493 UH |
348 | self.putx([1, ['Start of frame', 'SOF', 'S']]) |
349 | if can_rx != 0: | |
74c9bb3c | 350 | self.putx([16, ['Start of frame (SOF) must be a dominant bit']]) |
702fa251 | 351 | |
4b1813b4 UH |
352 | # Remember start of ID (see below). |
353 | elif bitnum == 1: | |
354 | self.ss_block = self.samplenum | |
355 | ||
702fa251 UH |
356 | # Bits 1-11: Identifier (ID[10..0]) |
357 | # The bits ID[10..4] must NOT be all recessive. | |
358 | elif bitnum == 11: | |
359 | self.id = int(''.join(str(d) for d in self.bits[1:]), 2) | |
534ae912 | 360 | s = '%d (0x%x)' % (self.id, self.id), |
74c9bb3c | 361 | self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']]) |
2fac4493 UH |
362 | if (self.id & 0x7f0) == 0x7f0: |
363 | self.putb([16, ['Identifier bits 10..4 must not be all recessive']]) | |
702fa251 UH |
364 | |
365 | # RTR or SRR bit, depending on frame type (gets handled later). | |
366 | elif bitnum == 12: | |
4b1813b4 UH |
367 | # self.putx([0, ['RTR/SRR: %d' % can_rx]]) # Debug only. |
368 | self.ss_bit12 = self.samplenum | |
702fa251 UH |
369 | |
370 | # Bit 13: Identifier extension (IDE) bit | |
371 | # Standard frame: dominant, extended frame: recessive | |
372 | elif bitnum == 13: | |
373 | ide = self.frame_type = 'standard' if can_rx == 0 else 'extended' | |
74c9bb3c | 374 | self.putx([6, ['Identifier extension bit: %s frame' % ide, |
534ae912 | 375 | 'IDE: %s frame' % ide, 'IDE']]) |
702fa251 UH |
376 | |
377 | # Bits 14-X: Frame-type dependent, passed to the resp. handlers. | |
378 | elif bitnum >= 14: | |
379 | if self.frame_type == 'standard': | |
380 | done = self.decode_standard_frame(can_rx, bitnum) | |
381 | else: | |
382 | done = self.decode_extended_frame(can_rx, bitnum) | |
383 | ||
384 | # The handlers return True if a frame ended (EOF). | |
385 | if done: | |
386 | return | |
387 | ||
388 | # After a frame there are 3 intermission bits (recessive). | |
389 | # After these bits, the bus is considered free. | |
390 | ||
391 | self.curbit += 1 | |
392 | ||
64d87119 | 393 | def decode(self): |
21cda951 UH |
394 | if not self.samplerate: |
395 | raise SamplerateError('Cannot decode without samplerate.') | |
702fa251 | 396 | |
64d87119 | 397 | while True: |
702fa251 UH |
398 | # State machine. |
399 | if self.state == 'IDLE': | |
400 | # Wait for a dominant state (logic 0) on the bus. | |
64d87119 | 401 | (can_rx,) = self.wait({0: 'l'}) |
702fa251 | 402 | self.sof = self.samplenum |
45a50880 | 403 | self.dom_edge_seen(force = True) |
702fa251 UH |
404 | self.state = 'GET BITS' |
405 | elif self.state == 'GET BITS': | |
406 | # Wait until we're in the correct bit/sampling position. | |
64d87119 | 407 | pos = self.get_sample_point(self.curbit) |
45a50880 GS |
408 | (can_rx,) = self.wait([{'skip': pos - self.samplenum}, {0: 'f'}]) |
409 | if self.matched[1]: | |
410 | self.dom_edge_seen() | |
411 | if self.matched[0]: | |
412 | self.handle_bit(can_rx) | |
413 | self.bit_sampled() |