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702fa251 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
702fa251 | 3 | ## |
e20f455c | 4 | ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de> |
702fa251 UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | # CAN protocol decoder | |
22 | ||
23 | import sigrokdecode as srd | |
24 | ||
25 | class Decoder(srd.Decoder): | |
26 | api_version = 1 | |
27 | id = 'can' | |
28 | name = 'CAN' | |
9e1437a0 | 29 | longname = 'Controller Area Network' |
702fa251 UH |
30 | desc = 'Field bus protocol for distributed realtime control.' |
31 | license = 'gplv2+' | |
32 | inputs = ['logic'] | |
33 | outputs = ['can'] | |
34 | probes = [ | |
35 | {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'}, | |
36 | ] | |
37 | optional_probes = [] | |
38 | options = { | |
39 | 'bitrate': ['Bitrate', 1000000], # 1Mbit/s | |
40 | 'sample_point': ['Sample point', 70], # 70% | |
41 | } | |
42 | annotations = [ | |
43 | ['Text', 'Human-readable text'], | |
44 | ['Warnings', 'Human-readable warnings'], | |
45 | ] | |
46 | ||
47 | def __init__(self, **kwargs): | |
48 | self.reset_variables() | |
49 | ||
50 | def start(self, metadata): | |
51 | # self.out_proto = self.add(srd.OUTPUT_PROTO, 'can') | |
52 | self.out_ann = self.add(srd.OUTPUT_ANN, 'can') | |
53 | ||
54 | self.samplerate = metadata['samplerate'] | |
55 | self.bit_width = float(self.samplerate) / float(self.options['bitrate']) | |
56 | self.bitpos = (self.bit_width / 100.0) * self.options['sample_point'] | |
57 | ||
58 | def report(self): | |
59 | pass | |
60 | ||
4b1813b4 UH |
61 | # Generic helper for CAN bit annotations. |
62 | def putg(self, ss, es, data): | |
63 | left, right = int(self.bitpos), int(self.bit_width - self.bitpos) | |
64 | self.put(ss - left, es + right, self.out_ann, data) | |
65 | ||
66 | # Single-CAN-bit annotation using the current samplenum. | |
e20f455c | 67 | def putx(self, data): |
4b1813b4 UH |
68 | self.putg(self.samplenum, self.samplenum, data) |
69 | ||
70 | # Single-CAN-bit annotation using the samplenum of CAN bit 12. | |
71 | def put12(self, data): | |
72 | self.putg(self.ss_bit12, self.ss_bit12, data) | |
73 | ||
74 | # Multi-CAN-bit annotation from self.ss_block to current samplenum. | |
75 | def putb(self, data): | |
76 | self.putg(self.ss_block, self.samplenum, data) | |
e20f455c | 77 | |
702fa251 UH |
78 | def reset_variables(self): |
79 | self.state = 'IDLE' | |
80 | self.sof = self.frame_type = self.dlc = None | |
81 | self.rawbits = [] # All bits, including stuff bits | |
82 | self.bits = [] # Only actual CAN frame bits (no stuff bits) | |
83 | self.curbit = 0 # Current bit of CAN frame (bit 0 == SOF) | |
84 | self.last_databit = 999 # Positive value that bitnum+x will never match | |
4b1813b4 UH |
85 | self.ss_block = None |
86 | self.ss_bit12 = None | |
87 | self.ss_databytebits = [] | |
702fa251 UH |
88 | |
89 | # Return True if we reached the desired bit position, False otherwise. | |
90 | def reached_bit(self, bitnum): | |
91 | bitpos = int(self.sof + (self.bit_width * bitnum) + self.bitpos) | |
92 | if self.samplenum >= bitpos: | |
93 | return True | |
94 | return False | |
95 | ||
96 | def is_stuff_bit(self): | |
97 | # CAN uses NRZ encoding and bit stuffing. | |
98 | # After 5 identical bits, a stuff bit of opposite value is added. | |
99 | last_6_bits = self.rawbits[-6:] | |
100 | if last_6_bits not in ([0, 0, 0, 0, 0, 1], [1, 1, 1, 1, 1, 0]): | |
101 | return False | |
102 | ||
103 | # Stuff bit. Keep it in self.rawbits, but drop it from self.bits. | |
e20f455c | 104 | self.putx([0, ['Stuff bit: %d' % self.rawbits[-1]]]) |
702fa251 UH |
105 | self.bits.pop() # Drop last bit. |
106 | return True | |
107 | ||
108 | def is_valid_crc(self, crc_bits): | |
109 | return True # TODO | |
110 | ||
111 | def decode_error_frame(self, bits): | |
112 | pass # TODO | |
113 | ||
114 | def decode_overload_frame(self, bits): | |
115 | pass # TODO | |
116 | ||
117 | # Both standard and extended frames end with CRC, CRC delimiter, ACK, | |
118 | # ACK delimiter, and EOF fields. Handle them in a common function. | |
119 | # Returns True if the frame ended (EOF), False otherwise. | |
120 | def decode_frame_end(self, can_rx, bitnum): | |
121 | ||
4b1813b4 UH |
122 | # Remember start of CRC sequence (see below). |
123 | if bitnum == (self.last_databit + 1): | |
124 | self.ss_block = self.samplenum | |
125 | ||
702fa251 | 126 | # CRC sequence (15 bits) |
4b1813b4 | 127 | elif bitnum == (self.last_databit + 15): |
702fa251 UH |
128 | x = self.last_databit + 1 |
129 | crc_bits = self.bits[x:x + 15 + 1] | |
130 | self.crc = int(''.join(str(d) for d in crc_bits), 2) | |
4b1813b4 | 131 | self.putb([0, ['CRC: 0x%04x' % self.crc]]) |
702fa251 | 132 | if not self.is_valid_crc(crc_bits): |
4b1813b4 | 133 | self.putb([0, ['CRC is invalid']]) |
702fa251 UH |
134 | |
135 | # CRC delimiter bit (recessive) | |
136 | elif bitnum == (self.last_databit + 16): | |
e20f455c | 137 | self.putx([0, ['CRC delimiter: %d' % can_rx]]) |
702fa251 UH |
138 | |
139 | # ACK slot bit (dominant: ACK, recessive: NACK) | |
140 | elif bitnum == (self.last_databit + 17): | |
141 | ack = 'ACK' if can_rx == 0 else 'NACK' | |
e20f455c | 142 | self.putx([0, ['ACK slot: %s' % ack]]) |
702fa251 UH |
143 | |
144 | # ACK delimiter bit (recessive) | |
145 | elif bitnum == (self.last_databit + 18): | |
e20f455c | 146 | self.putx([0, ['ACK delimiter: %d' % can_rx]]) |
702fa251 | 147 | |
4b1813b4 UH |
148 | # Remember start of EOF (see below). |
149 | elif bitnum == (self.last_databit + 19): | |
150 | self.ss_block = self.samplenum | |
151 | ||
702fa251 UH |
152 | # End of frame (EOF), 7 recessive bits |
153 | elif bitnum == (self.last_databit + 25): | |
4b1813b4 | 154 | self.putb([0, ['End of frame', 'EOF']]) |
702fa251 UH |
155 | self.reset_variables() |
156 | return True | |
157 | ||
158 | return False | |
159 | ||
160 | # Returns True if the frame ended (EOF), False otherwise. | |
161 | def decode_standard_frame(self, can_rx, bitnum): | |
162 | ||
163 | # Bit 14: RB0 (reserved bit) | |
164 | # Has to be sent dominant, but receivers should accept recessive too. | |
165 | if bitnum == 14: | |
e20f455c | 166 | self.putx([0, ['RB0: %d' % can_rx]]) |
702fa251 UH |
167 | |
168 | # Bit 12: Remote transmission request (RTR) bit | |
169 | # Data frame: dominant, remote frame: recessive | |
170 | # Remote frames do not contain a data field. | |
171 | rtr = 'remote' if self.bits[12] == 1 else 'data' | |
4b1813b4 UH |
172 | self.put12([0, ['RTR: %s frame' % rtr]]) |
173 | ||
174 | # Remember start of DLC (see below). | |
175 | elif bitnum == 15: | |
176 | self.ss_block = self.samplenum | |
702fa251 UH |
177 | |
178 | # Bits 15-18: Data length code (DLC), in number of bytes (0-8). | |
179 | elif bitnum == 18: | |
180 | self.dlc = int(''.join(str(d) for d in self.bits[15:18 + 1]), 2) | |
4b1813b4 | 181 | self.putb([0, ['DLC: %d' % self.dlc]]) |
702fa251 UH |
182 | self.last_databit = 18 + (self.dlc * 8) |
183 | ||
4b1813b4 UH |
184 | # Remember all databyte bits, except the very last one. |
185 | elif bitnum in range(19, self.last_databit): | |
186 | self.ss_databytebits.append(self.samplenum) | |
187 | ||
702fa251 UH |
188 | # Bits 19-X: Data field (0-8 bytes, depending on DLC) |
189 | # The bits within a data byte are transferred MSB-first. | |
190 | elif bitnum == self.last_databit: | |
4b1813b4 | 191 | self.ss_databytebits.append(self.samplenum) # Last databyte bit. |
702fa251 UH |
192 | for i in range(self.dlc): |
193 | x = 18 + (8 * i) + 1 | |
194 | b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) | |
4b1813b4 UH |
195 | ss = self.ss_databytebits[i * 8] |
196 | es = self.ss_databytebits[((i + 1) * 8) - 1] | |
197 | self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b)]]) | |
198 | self.ss_databytebits = [] | |
702fa251 UH |
199 | |
200 | elif bitnum > self.last_databit: | |
201 | return self.decode_frame_end(can_rx, bitnum) | |
202 | ||
203 | return False | |
204 | ||
205 | # Returns True if the frame ended (EOF), False otherwise. | |
206 | def decode_extended_frame(self, can_rx, bitnum): | |
207 | ||
4b1813b4 UH |
208 | # Remember start of EID (see below). |
209 | if bitnum == 14: | |
210 | self.ss_block = self.samplenum | |
211 | ||
702fa251 | 212 | # Bits 14-31: Extended identifier (EID[17..0]) |
4b1813b4 | 213 | elif bitnum == 31: |
702fa251 | 214 | self.eid = int(''.join(str(d) for d in self.bits[14:]), 2) |
4b1813b4 | 215 | self.putb([0, ['Extended ID: %d (0x%x)' % (self.eid, self.eid)]]) |
702fa251 UH |
216 | |
217 | self.fullid = self.id << 18 | self.eid | |
4b1813b4 | 218 | self.putb([0, ['Full ID: %d (0x%x)' % (self.fullid, self.fullid)]]) |
702fa251 UH |
219 | |
220 | # Bit 12: Substitute remote request (SRR) bit | |
4b1813b4 | 221 | self.put12([0, ['SRR: %d' % self.bits[12]]]) |
702fa251 UH |
222 | |
223 | # Bit 32: Remote transmission request (RTR) bit | |
224 | # Data frame: dominant, remote frame: recessive | |
225 | # Remote frames do not contain a data field. | |
226 | if bitnum == 32: | |
227 | rtr = 'remote' if can_rx == 1 else 'data' | |
e20f455c | 228 | self.putx([0, ['RTR: %s frame' % rtr]]) |
702fa251 UH |
229 | |
230 | # Bit 33: RB1 (reserved bit) | |
231 | elif bitnum == 33: | |
e20f455c | 232 | self.putx([0, ['RB1: %d' % can_rx]]) |
702fa251 UH |
233 | |
234 | # Bit 34: RB0 (reserved bit) | |
235 | elif bitnum == 34: | |
e20f455c | 236 | self.putx([0, ['RB0: %d' % can_rx]]) |
702fa251 | 237 | |
4b1813b4 UH |
238 | # Remember start of DLC (see below). |
239 | elif bitnum == 35: | |
240 | self.ss_block = self.samplenum | |
241 | ||
702fa251 UH |
242 | # Bits 35-38: Data length code (DLC), in number of bytes (0-8). |
243 | elif bitnum == 38: | |
244 | self.dlc = int(''.join(str(d) for d in self.bits[35:38 + 1]), 2) | |
4b1813b4 | 245 | self.putb([0, ['DLC: %d' % self.dlc]]) |
702fa251 UH |
246 | self.last_databit = 38 + (self.dlc * 8) |
247 | ||
4b1813b4 UH |
248 | # Remember all databyte bits, except the very last one. |
249 | elif bitnum in range(39, self.last_databit): | |
250 | self.ss_databytebits.append(self.samplenum) | |
251 | ||
702fa251 UH |
252 | # Bits 39-X: Data field (0-8 bytes, depending on DLC) |
253 | # The bits within a data byte are transferred MSB-first. | |
254 | elif bitnum == self.last_databit: | |
4b1813b4 | 255 | self.ss_databytebits.append(self.samplenum) # Last databyte bit. |
702fa251 UH |
256 | for i in range(self.dlc): |
257 | x = 38 + (8 * i) + 1 | |
258 | b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) | |
4b1813b4 UH |
259 | ss = self.ss_databytebits[i * 8] |
260 | es = self.ss_databytebits[((i + 1) * 8) - 1] | |
261 | self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b)]]) | |
262 | self.ss_databytebits = [] | |
702fa251 UH |
263 | |
264 | elif bitnum > self.last_databit: | |
265 | return self.decode_frame_end(can_rx, bitnum) | |
266 | ||
267 | return False | |
268 | ||
269 | def handle_bit(self, can_rx): | |
270 | self.rawbits.append(can_rx) | |
271 | self.bits.append(can_rx) | |
272 | ||
273 | # Get the index of the current CAN frame bit (without stuff bits). | |
274 | bitnum = len(self.bits) - 1 | |
275 | ||
276 | # For debugging. | |
e20f455c UH |
277 | # self.putx([0, ['Bit %d (CAN bit %d): %d' % \ |
278 | # (self.curbit, bitnum, can_rx)]]) | |
702fa251 UH |
279 | |
280 | # If this is a stuff bit, remove it from self.bits and ignore it. | |
281 | if self.is_stuff_bit(): | |
282 | self.curbit += 1 # Increase self.curbit (bitnum is not affected). | |
283 | return | |
284 | ||
285 | # Bit 0: Start of frame (SOF) bit | |
286 | if bitnum == 0: | |
287 | if can_rx == 0: | |
e20f455c | 288 | self.putx([0, ['Start of frame', 'SOF']]) |
702fa251 | 289 | else: |
e20f455c | 290 | self.putx([1, ['Start of frame (SOF) must be a dominant bit']]) |
702fa251 | 291 | |
4b1813b4 UH |
292 | # Remember start of ID (see below). |
293 | elif bitnum == 1: | |
294 | self.ss_block = self.samplenum | |
295 | ||
702fa251 UH |
296 | # Bits 1-11: Identifier (ID[10..0]) |
297 | # The bits ID[10..4] must NOT be all recessive. | |
298 | elif bitnum == 11: | |
299 | self.id = int(''.join(str(d) for d in self.bits[1:]), 2) | |
4b1813b4 | 300 | self.putb([0, ['ID: %d (0x%x)' % (self.id, self.id)]]) |
702fa251 UH |
301 | |
302 | # RTR or SRR bit, depending on frame type (gets handled later). | |
303 | elif bitnum == 12: | |
4b1813b4 UH |
304 | # self.putx([0, ['RTR/SRR: %d' % can_rx]]) # Debug only. |
305 | self.ss_bit12 = self.samplenum | |
702fa251 UH |
306 | |
307 | # Bit 13: Identifier extension (IDE) bit | |
308 | # Standard frame: dominant, extended frame: recessive | |
309 | elif bitnum == 13: | |
310 | ide = self.frame_type = 'standard' if can_rx == 0 else 'extended' | |
e20f455c | 311 | self.putx([0, ['IDE: %s frame' % ide]]) |
702fa251 UH |
312 | |
313 | # Bits 14-X: Frame-type dependent, passed to the resp. handlers. | |
314 | elif bitnum >= 14: | |
315 | if self.frame_type == 'standard': | |
316 | done = self.decode_standard_frame(can_rx, bitnum) | |
317 | else: | |
318 | done = self.decode_extended_frame(can_rx, bitnum) | |
319 | ||
320 | # The handlers return True if a frame ended (EOF). | |
321 | if done: | |
322 | return | |
323 | ||
324 | # After a frame there are 3 intermission bits (recessive). | |
325 | # After these bits, the bus is considered free. | |
326 | ||
327 | self.curbit += 1 | |
328 | ||
329 | def decode(self, ss, es, data): | |
330 | for (self.samplenum, pins) in data: | |
331 | ||
332 | (can_rx,) = pins | |
333 | ||
334 | # State machine. | |
335 | if self.state == 'IDLE': | |
336 | # Wait for a dominant state (logic 0) on the bus. | |
337 | if can_rx == 1: | |
338 | continue | |
339 | self.sof = self.samplenum | |
702fa251 UH |
340 | self.state = 'GET BITS' |
341 | elif self.state == 'GET BITS': | |
342 | # Wait until we're in the correct bit/sampling position. | |
343 | if not self.reached_bit(self.curbit): | |
344 | continue | |
345 | self.handle_bit(can_rx) | |
346 | else: | |
347 | raise Exception("Invalid state: %s" % self.state) | |
348 |