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1 | ## |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2020 Analog Devices Inc. | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 3 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | ## | |
19 | ||
20 | import sigrokdecode as srd | |
21 | ||
22 | modes = { | |
23 | 0: ['Normal Mode', 'Normal', 'Norm', 'N'], | |
24 | 1: ['Power Down Mode', 'Power Down', 'PD'], | |
25 | 2: ['Power Up Mode', 'Power Up', 'PU'], | |
26 | } | |
27 | ||
b5d9eaab | 28 | input_voltage_format = ['%.6fV', '%.2fV'] |
487b3d84 TP |
29 | |
30 | validation = { | |
31 | 'invalid': ['Invalid data', 'Invalid', 'N/A'], | |
32 | 'incomplete': ['Incomplete conversion', 'Incomplete', 'I'], | |
33 | 'complete': ['Complete conversion', 'Complete', 'C'], | |
34 | } | |
35 | ||
36 | class Decoder(srd.Decoder): | |
37 | api_version = 3 | |
38 | id = 'ad79x0' | |
39 | name = 'AD79x0' | |
40 | longname = 'Analog Devices AD79x0' | |
41 | desc = 'Analog Devices AD7910/AD7920 12-bit ADC.' | |
42 | license = 'gplv2+' | |
43 | inputs = ['spi'] | |
44 | outputs = [] | |
f40e0a73 | 45 | tags = ['IC', 'Analog/digital'] |
487b3d84 TP |
46 | annotations = ( |
47 | ('mode', 'Mode'), | |
2e01ea8b | 48 | ('voltage', 'Voltage'), |
487b3d84 TP |
49 | ('validation', 'Validation'), |
50 | ) | |
51 | annotation_rows = ( | |
2e01ea8b UH |
52 | ('modes', 'Modes', (0,)), |
53 | ('voltages', 'Voltages', (1,)), | |
487b3d84 TP |
54 | ('data_validation', 'Data validation', (2,)), |
55 | ) | |
56 | options = ( | |
5b6fb5ae | 57 | {'id': 'vref', 'desc': 'Reference voltage (V)', 'default': 1.5}, |
487b3d84 TP |
58 | ) |
59 | ||
60 | def __init__(self,): | |
61 | self.reset() | |
62 | ||
63 | def reset(self): | |
64 | self.samplerate = 0 | |
65 | self.samples_bit = -1 | |
66 | self.ss = -1 | |
67 | self.start_sample = 0 | |
68 | self.previous_state = 0 | |
69 | self.data = 0 | |
70 | ||
71 | def metadata(self, key, value): | |
72 | if key == srd.SRD_CONF_SAMPLERATE: | |
73 | self.samplerate = value | |
74 | ||
75 | def start(self): | |
76 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
77 | ||
78 | def put_validation(self, pos, msg): | |
79 | self.put(pos[0], pos[1], self.out_ann, [2, validation[msg]]) | |
80 | ||
81 | def put_data(self, pos, input_voltage): | |
82 | ann = [] | |
83 | for format in input_voltage_format: | |
84 | ann.append(format % input_voltage) | |
85 | self.put(pos[0], pos[1], self.out_ann, [1, ann]) | |
86 | ||
87 | def put_mode(self, pos, msg): | |
88 | self.put(pos[0], pos[1], self.out_ann, [0, modes[msg]]) | |
89 | ||
90 | def decode(self, ss, es, data): | |
91 | ptype = data[0] | |
92 | ||
93 | if ptype == 'CS-CHANGE': | |
94 | cs_old, cs_new = data[1:] | |
95 | if cs_old is not None and cs_old == 0 and cs_new == 1: | |
96 | if self.samples_bit == -1: | |
97 | return | |
98 | self.data >>= 1 | |
99 | nb_bits = (ss - self.ss) // self.samples_bit | |
100 | if nb_bits >= 10: | |
101 | if self.data == 0xFFF: | |
102 | self.put_mode([self.start_sample, es], 2) | |
103 | self.previous_state = 0 | |
104 | self.put_validation([self.start_sample, es], 'invalid') | |
105 | else: | |
106 | self.put_mode([self.start_sample, es], 0) | |
107 | if nb_bits == 16: | |
108 | self.put_validation([self.start_sample, es], 'complete') | |
109 | elif nb_bits < 16: | |
110 | self.put_validation([self.start_sample, es], 'incomplete') | |
5b6fb5ae | 111 | vin = (self.data / ((2**12) - 1)) * self.options['vref'] |
487b3d84 TP |
112 | self.put_data([self.start_sample, es], vin) |
113 | elif nb_bits < 10: | |
114 | self.put_mode([self.start_sample, es], 1) | |
115 | self.previous_state = 1 | |
116 | self.put_validation([self.start_sample, es], 'invalid') | |
117 | ||
118 | self.ss = -1 | |
119 | self.samples_bit = -1 | |
120 | self.data = 0 | |
121 | elif cs_old is not None and cs_old == 1 and cs_new == 0: | |
122 | self.start_sample = ss | |
123 | self.samples_bit = -1 | |
124 | ||
125 | elif ptype == 'BITS': | |
126 | if data[2] is None: | |
127 | return | |
128 | miso = data[2] | |
129 | if self.samples_bit == -1: | |
130 | self.samples_bit = miso[0][2] - miso[0][1] | |
131 | ||
132 | if self.ss == -1: | |
133 | self.ss = ss | |
134 | ||
135 | for bit in reversed(miso): | |
136 | self.data = self.data | bit[0] | |
137 | self.data <<= 1 |